
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
106
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
register file compilation (continued)
Table 24. Register File Compilation (Continued)
ADDR
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
REG
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SERIAL PERIPHERAL INTERFACE (SPI) CONFIGURATION CONTROL REGISTERS (CONTINUED)
07047h
RXB15
RXB14
RXB13
RXB12
RXB11
RXB10
RXB9
RXB8
SPIRXBUF
RXB7
RXB6
RXB5
RXB4
RXB3
RXB2
RXB1
RXB0
07048h
TXB15
TXB14
TXB13
TXB12
TXB11
TXB10
TXB9
TXB8
SPITXBUF
TXB7
TXB6
TXB5
TXB4
TXB3
TXB2
TXB1
TXB0
07049h
SDAT15
SDAT14
SDAT13
SDAT12
SDAT11
SDAT10
SDAT9
SDAT8
SPIDAT
SDAT7
SDAT6
SDAT5
SDAT4
SDAT3
SDAT2
SDAT1
SDAT0
0704Ah
Reserved
0704Eh
0704Fh
—
SPI
PRIORITY
SPI
SUSP SOFT
SPI
SUSP FREE
—
—
—
—
SPIPRI
SERIAL COMMUNICATIONS INTERFACE (SCI) CONFIGURATION CONTROL REGISTERS
07050h
STOP
BITS
EVEN/ODD
PARITY
PARITY
ENABLE
LOOP BACK
ENA
ADDR/IDLE
MODE
SCI
CHAR2
SCI
CHAR1
SCI
CHAR0
SCICCR
07051h
—
RX ERR
INT ENA
SW RESET
—
TXWAKE
SLEEP
TXENA
RXENA
SCICTL1
07052h
BAUD15
(MSB)
BAUD14
BAUD13
BAUD12
BAUD11
BAUD10
BAUD9
BAUD8
SCIHBAUD
07053h
BAUD7
BAUD6
BAUD5
BAUD4
BAUD3
BAUD2
BAUD1
BAUD0
(LSB)
SCILBAUD
07054h
TXRDY
TX EMPTY
—
—
—
—
RX/BK
INT ENA
TX
INT ENA
SCICTL2
07055h
RX ERROR
RXRDY
BRKDT
FE
OE
PE
RXWAKE
—
SCIRXST
07056h
ERXDT7
ERXDT6
ERXDT5
ERXDT4
ERXDT3
ERXDT2
ERXDT1
ERXDT0
SCIRXEMU
07057h
RXDT7
RXDT6
RXDT5
RXDT4
RXDT3
RXDT2
RXDT1
RXDT0
SCIRXBUF
07058h
Reserved
07059h
TXDT7
TXDT6
TXDT5
TXDT4
TXDT3
TXDT2
TXDT1
TXDT0
SCITXBUF
0705Ah
to
0705Eh
Reserved
0705Fh
—
SCITX
PRIORITY
SCIRX
PRIORITY
SCI
SOFT
SCI
FREE
—
—
—
SCIPRI
07060h
to
0706Fh
Reserved
EXTERNAL INTERRUPT CONTROL REGISTERS
07070h
XINT1
FLAG
—
—
—
—
—
—
—
XINT1CR
—
—
—
—
—
XINT1
POLARITY
XINT1
PRIORITY
XINT1
ENA
07071h
XINT2
FLAG
—
—
—
—
—
—
—
XINT2CR
—
—
—
—
—
XINT2
POLARITY
XINT2
PRIORITY
XINT2
ENA