參數(shù)資料
型號: TMS320C241PGS
元件分類: 數(shù)字信號處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數(shù)字信號處理器
文件頁數(shù): 102/116頁
文件大小: 1485K
代理商: TMS320C241PGS
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
102
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
internal ADC module timings (see Figure 43)
MIN
MAX
UNIT
tc(AD)
tw(SHC)
tw(SH)
tw(C)
td(SOC-SH)
td(EOC-FIFO)
td(ADCINT)
The total sample/hold and conversion time is determined by the summation of td(SOC-SH), tw(SH), tw(C), and td(EOC-FIFO).
Start of conversion is signaled by the ADCIMSTART bit (ADCTRL1.13) or the ADCSOC bit (ADCTRL1.0) set in software, the external start signal
active (ADCSOC), or internal EVSOC signal active.
Cycle time, ADC prescaled clock
Pulse duration, total sample/hold and conversion time
50
ns
900
ns
Pulse duration, sample and hold time
3tc(AD)
10tc(AD)
3tc(CO)
2tc(CO)
2tc(CO)
ns
Pulse duration, total conversion time
Delay time, start of conversion to beginning of sample and hold
ns
ns
Delay time, end of conversion to data loaded into result FIFO
ns
Delay time, ADC flag to ADC interrupt
ns
0
3
2
4
5
1
tw(C)
6
7
8
tc(AD)
ADC Clock
Analog Input
Bit Converted
td(SOC–SH)
EOC/Convert
Internal Start/
Sample Hold
Start of Convert
XFR to FIFO
tw(SHC)
áááááááááááááááááááááááááááá
áááááááááááááááááááááááááááá
td(EOC–FIFO)
9
tw(SH)
td(ADCINT)
Figure 43. Analog-to-Digital Internal Module Timing
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