
TMC2192
PRODUCT SPECIFICATION
34
P
VBI Ped Enable Registers
VBIPEDEM
VBIPEDEL
VBIPEDOM
VBIPEDOL
HVA
14
15
16
17
17
7-0
7-0
7-0
7-1
0
VBI Pedestal Enable, Even Fields
VBI Pedestal Enable, Even Fields
VBI Pedestal Enable, Odd Fields
VBI Pedestal Enable, Odd Fields
Horizontal and Vertical Sync 
Alignment
Vertical Blanking Interval Enable Registers
7
Reserved
Program Low
6
GLKCTL1
Genlock Control Register 1
5
GLKCTL0
Genlock Control Register 0
4-0
VBIENF1
VBI Active Video Enable, Field 1
7
SHORT
Test Register
6
T512
EH/SL Offset Control Bit
5
HALFEN
Half Line Enable
4-0
VBIENF2
VBI Active Video Enable, Field 2
Pedestal Height Register
7
Reserved
Program Low
6-0
PEDHGT1
Composite Pedestal Height
Closed Caption Registers
7-0
CCD1
First Byte of CC Data
7-0
CCD2
Second Byte of CC Data
7
CCON
Enable CC Data Packet
6
CCRTS
Request to Send Data
5
CCPAR
Auto Parity Generation
4
CCFLD
CC Field Select
3-0
CCLINE
CC Line Select
Timing Registers
7-0
PDCNT
Pixel Data Control Start
7-0
SY
Horizontal Sync Tip Duration
7-0
BR
Breezeway Duration
7-0
BU
Burst Duration
7-0
CBP
Color Back Porch Duration
18
18
18
18
19
19
19
19
1A
1A
1C
1D
1E
1E
1E
1E
1E
1F
20
21
22
23
Table 22. Control Register Map 
(continued)
Reg Bit
Mnemonic
Function
24
7-0
XBP
Extended Color Back Porch 
Duration
Active Video Region Duration
Active Video Region 2nd Half 
Line Duration
Active Video Region 1st Half 
Line Duration
Equalization Pulse Low Duration
Equalization Pulse High 
Duration
Vertical Sync Pulse Low 
Duration
Vertical Sync Pulse High 
Duration
Front Proch Duration
Extended Color Back Porch 
Duration
Active Video Duration
Active Video Region 1st Half 
Line Duration
Active Video Region 2nd Half 
Line Duration
Field Identification (read only)
Line Type Identification (read 
only)
Color Bar Duration
Color Space Matrix Registers
MCF1L
Matrix Coefficient #1
Reserved
Program Low
Reserved
Program Low
MCF2L
Matrix Coefficient #2
Reserved
Program Low
MCF3L
Matrix Coefficient #3
Reserved
Program Low
Reserved
Program Low
25
26
7-0
7-0
VA
VC
27
7-0
VB
28
29
7-0
7-0
EL
EH
2A
7-0
SL
2B
7-0
SH
2C
2D
7-0
7-6
FP
XBP
2D
2D
5-4
3-2
VA
VB
2D
1-0
VC
2E
2E
7-5
4-0
FIELD
LTYPE
2F
7-0
CBL
30
31
32
33
34
35
36
37
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
Table 22. Control Register Map 
(continued)
Reg Bit
Mnemonic
Function