參數(shù)資料
型號(hào)： TMC2192
廠商： Fairchild Semiconductor Corporation
英文描述： 10 Bit Video Encoder(10位視頻編碼器)
中文描述： 10位視頻編碼器（10位視頻編碼器）
文件頁(yè)數(shù)： 23/72頁(yè)
文件大小： 396K
代理商： TMC2192
PRODUCT SPECIFICATION
TMC2192
23
P
Burst Envelope
The TMC2192 includes the ability to adjust the burst ampli-
tude and the shape of the burst. The Control Registers
BRSTFULL, BRST1 and BRST2 hold the magnitude of the
burst vector. BRSTFULL is the maximum amplitude of the
burst vector. BRST1 and BRST2 determine the intermediate
values of the burst vector for the burst envelope shaping. A 5
pixel burst envelope shaping occurs at the rising and falling
edges of burst. At the rising edge of burst the next 5 pixels
have the following weighting; BRSTFULL – BRST1,
BRSTFULL – BRST2, BRSTFULL/2, BRST2, and BRST1.
At the falling edge of burst the next 5 pixels have the follow-
ing weighting; BRST1, BRST2, BRSTFULL/2, BRSTFULL
– BRST2, and BRSTFULL – BRST1. With this flexibility
the user determine the shape, amplitude and width of the
burst signal.
Figure 15. Burst Envelope
Color-Difference Low-Pass Filters
The chrominance portion of a composite video signal must
be sufficiently bandlimited to avoid cross-color and cross-
luminance distortion, and to preclude exceeding the allow-
able bandwidth of a video channel.
The color-difference low-pass filters on the TMC2192
establish chrominance bandwidths which meet the specifica-
tions outlined in CCIR Report 624-3, Table II, Item 2.6, for
system I over a range of pixel rates from 12.27 Mpps to
14.75 Mpps. Equal bandwidth is established for both color-
difference channels.
Figure 16. Gaussian Filter Response
Sync and Pedestal Insertion
Control Registers for this section
Pedestal Enable
The TMC2192 has the ability to independently select lines
for pedestal insertion during the vertical blanking interval
(VBI). For 525-line systems and using the NTSC line num-
bering convention, in which the first vertical serration is on
line 4 for field 1 and line 266 for field 2, the vertical interval
lines map to the control registers VBIPEDxy as shown in
Table 15.
BRSTFULL
BRST1
BRST2
BRSTFULL/2
BRSTFULL - BRST2
BRSTFULL - BRST1
BLANK
BU
65-6294-18
Address
0x06
0x11
0x14
0x15
0x16
0x17
0x1A
0x3F
Bit(s)
7-6
5
7-0
7-0
7-0
7-0
6-0
3
Name
MODE
COMP2DB
VBIPEDEM
VBIPEDEL
VBIPEDOM
VBIPENOL
PEDHGT1
C2DB_OFF
-80
-70
-60
-50
-40
-30
-20
-10
0
0
0.1
0.2
0.3
0.4
0.5
6
Normalized Frequency (Pixel rate)
A
Table 12. Line by Line Pedestal Enable
Bit
VBIPEDEL
VBIPEDEM
VBIPEDOL
VBIPEDOM
7
6
5
4
3
2
1
0
17
25*
279
287*
16
24
278
286
15
23
277
285
14
22
276
284
13
21
275
283
12
20
274
282
11
19
273
281
10
18
280
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參數(shù)描述
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