
TMC2192
PRODUCT SPECIFICATION
30
P
In read mode, the address is accompanied by a HIGH on the 
R/W pin during a falling edge of CS. The data output pins go 
to a low-impedance state t
DOZ
 after CS falls. Valid data are 
present on D7-0 t
DOM
 after the falling edge of CS. Because 
this port operates asynchronously with the pixel timing, 
there is an uncertainty in this data valid output delay of one 
PXCK period. This uncertainty does not apply to t
DOZ
.
Writing data to specific control registers of the TMC2192 
requires that the 8 bit address of the control register of inter-
est be written prior to the data. This control register address 
is the base address for subsequent write operations. The base 
address auto increments by one for each byte of data written 
after the data byte intended for the base address. If more 
bytes are transferred than there are available addresses, the 
address will not increment and remain at its maximum value 
of 4Ch.
Writing data to specific OLUT location of the TMC2192 
requires that the 8 bit address of the OLUT location of inter-
est be written prior to the data sequence. This OLUT loca-
tion address is the base address for subsequent write 
operations. The base address auto increments by one for 
each sequence of three (3) bytes of data written after the data 
byte intended for the base address. The sequence of data 
transfer is Y, C
b
, C
r
 , after the C
r
 byte is transferred the base 
address will increment by one (1). 
Figure 23. Microprocessor Parallel Port – Write Timing
Figure 24. Microprocessor Parallel Port – Read Timing
Table 20. Parallel Port Control
 A
1-0
 00
R/W
0
Action
Load D
7-0
 into Control Register 
pointer (block 0)
Read Control Register pointer on 
D
7-0
Load D
7-0
 into addressed OLUT 
Location pointer (block 0)
Read addressed OLUT Location 
pointer on D
7-0
.
Write D
7-0
 to addressed Control 
Register
Read addressed Control Register 
on D
7-0
Write D
7-0
 to addressed OLUT 
Location
Read addressed OLUT Location on 
D
7-0
 00
1
 01
0
 01
1
 10
0
 10
1
 11
0
 11
1
t
PWLCS
t
SA
t
SD
t
HA
t
HD
t
PWHCS
CS
65-6294-26
R/W
ADR
D
7-0
t
PWLCS
t
SA
t
DOM
t
HA
t
HOM
t
DOZ
t
PWHCS
CS
R/W
ADR
D
7-0
65-6294-27