參數資料
型號： TMC2081
廠商： Fairchild Semiconductor Corporation
英文描述： Digital Video Mixer(數字視頻混頻器)
中文描述： 數字視頻混合器（數字視頻混頻器）
文件頁數： 8/32頁
文件大?。?/td> 158K
代理商： TMC2081
TMC2081
PRODUCT SPECIFICATION
8
Table 10. GBR DAC Transfer Characteristic
with Pedestal (SETUP = H)
YC
B
C
R
Output
Data inputs are unsigned Ydata and offset-binary format
C
B
data and C
R
data. BLANK = L sets C
B
and C
R
outputs to
128, the value for zero chrominance data. YC
B
C
R
transfer
equations are:
Y = (Ydata + SETUP * 21) & BLANK + SYNC * 110
C
B
= (Cdata + SETUP * 21) & BLANK + 128 & !BLANK
C
R
= (Cdata + SETUP * 21) & BLANK + 128 & !BLANK
Sample outputs are listed in Table 11 and Table 12.
Table 11. YCrCb DAC Transfer Characteristic
without Pedestal (SETUP = L)
Table 12. YCrCb DAC Transfer Characteristic
with Pedestal (SETUP = H)
D/A
Input
Data
255
128
0
X
X
128
G
B or R
SYNC BLANK
1
1
1
1
0
0
IU
386
259
131
110
0
149
mV
1000
671
339
285
0
386
IU
276
149
21
0
0
149
mV
715
386
54
0
0
386
1
1
1
0
0
1
D/A
Input
Data
255
128
64
0
X
X
64
Y
C
B
or C
R
SYNC BLANK
1
1
1
1
1
0
0
IU
365
238
174
110
110
0
64
mV
1000
652
477
301
301
0
175
IU
255
128.
64
0
128
128
64
mV
699
351
175
0
351
351
175
1
1
1
1
0
0
1
D/A
Data
255
128
64
0
X
X
64
Y
C
B
or C
R
IU
276
149
85
21
149
149
85
SYNC BLANK
1
1
1
1
1
0
0
IU
386
259
195
131
110
0
85
mV
1000
670
505
339
285
0
220
mV
715
386
220
54
386
386
220
1
1
1
1
0
0
1
Dissolve and Crossfade Operation
Video transitions such as dissolve and fades may be
executed by direct
a
-channel control. Rate and start time for
the transition depends entirely upon the value of the
a
8-0
inputs. Transitions may be executed as quickly or slowly as
values are presented to the
a
-channel. Transitions may
remain partially executed by keeping
a
-values constant.
It is possible to mix modes, bringing data in either 444 or
422 format and outputting data in 422 or 444 format.
In the 444/444 mode (see Figure 7),
a
is applied to each
YC
B
C
R
or GBR pixel pair at the input of the mixer.
The YC
B
C
R
444 output is mixed at the full
a
rate.
In the 422/422 mode (see Figure 8),
a
mixes the Y compo-
nent of incoming PDA and PDB pixels. Only odd indexed
a
values mix C
B
C
R
components.
a
-values applied to C
B
C
R
change synchronously with C
B
data. Consequently, full
bandwidth
a
data is applied to the luminance channel but the
chrominance channel
a
values are decimated by dropping
the even values that are synchronous with C
R
data.
In the 422/444 mode (see Figure 9), YC
B
C
R
422 data is
accepted at the PDA and PDB port but the output at the
M
23-0
port is YC
B
C
R
444.
a
may change from pixel-to-pixel
with mixing at the M
23-0
outputs tracking both Y and C
B
C
R
.
Although odd values of C
B
and C
R
are repeated at half the
pixel rate,
a
transitions are applied to C
B
and C
R
at the pixel
rate.
Microprocessor Interface
Internal Control Registers, CLUT,
a
LUT, and the overlay
palette are accessed through a bi-directional microprocessor
port, D
7-0
. Table 13 shows how address bits, A
2-0
, select the
registers to be accessed.
Table 13. Microprocessor Port Address Map
A2-0
000
Action
RAM Address Register for CLUT,
a
LUT, and
overlay palette for write operations
Directs RAM R/W operations selected by the
two MSBs of Control Address Register
Reserved
RAM Address Register for CLUT,
a
LUT, and
overlay palette for read operations
Reserved
Directs Control Register R/W operations
selected by the four LSBs of the Control
Address Register
Mask Register (Default: Load with FF)
Control Address Register
001
010
011
100
101
110
111
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相關代理商/技術參數
參數描述
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