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參數(shù)資料
| 型號： | TMC2081 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Digital Video Mixer(數(shù)字視頻混頻器) |
| 中文描述： | 數(shù)字視頻混合器（數(shù)字視頻混頻器） |
| 文件頁數(shù)： | 12/32頁 |
| 文件大?。?/td> | 158K |
| 代理商： | TMC2081 |
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TMC2081
PRODUCT SPECIFICATION
12
Pin Descriptions
Name
Clock
CLK
Pin Number
Value
Pin Function Description
59
TTL
Clock Input.
TTL-compatible clock. All pixel data is registered on the
rising edge of CLK. CLK synchronizes the flow of pixel data through
the TMC2081 and the operation of the
a
-input.
Pixel I/O
PDA
23-0
21-44
TTL
A-Channel Pixel Inputs.
A-channel pixel inputs are registered on the
rising edge of CLK and specify which of the CLUT locations are
addressed after masking. The CLUT in the A-Channel may be
bypassed. PDA
7-0
are applied to all three CLUT sections when color-
index pixel data is used.
B-Channel Pixel Inputs.
B-channel pixel inputs are registered on the
rising edge of CLK and are applied to the mixer after color-space
conversion, and interpolation, if selected.
a
-Channel Inputs.
The
a
-channel inputs are registered on the rising
edge of CLK and control proportional mixing at pixel rates up to 40
Mpps.
a
8
acts as a key input, switching A- and B-channel pixel data on
a pixel-by-pixel basis.
a
0
is the LSB.
ABF Crosspoint Mux Control.
When enabled by setting the SMX
Control Register bits to 111, these inputs control the ABF Crosspoint
Switch which directs the A- or B-channel pixels or the fill color register
values to the V
1
or V
2
inputs to the mixer. SMX
2-0
input pins are
ignored when the SMX Control Register bits are not 111. SMX
2-0
are
registered on the rising edge of CLK. ABF Crosspoint Switch control is
according to the following:
PDB
23-0
72-95
TTL
a
8-0
45,46,49-55
TTL
SMX
2-0
56-58
TTL
OL
3-0
15,18-20
TTL
Overlay Inputs.
Overlay inputs select one of 15 overlay colors from
the PDA overlay palette. OL
3-0
are registered on the rising edge of
CLK. When PDA or overlay is enabled and OL
3-0
> 0, the contents of
the addressed palette are selected in place of the pixel data. Overlay
is inactive when OL
3-0
= 0
h
or when disabled via the Control Registers.
OL
0
is the LSB.
Mixed Pixel Outputs.
Mixer output or digital preview of the V
1
and V
2
Crosspoint Switch outputs are synchronized to the rising edge of CLK.
M
23-0
date is passed on for further processing (mixing, encoding, etc.).
Pipeline latency is 14 clock cycles.
M
23-0
96-103,
106-121
TTL
SMX
2-0
000
001
010
011
100
101
110
111
V
1
A
A
B
B
F
F
-
-
V
2
B
F
A
F
A
B
-
-
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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