參數(shù)資料
型號(hào)： TMC2081
廠商： Fairchild Semiconductor Corporation
英文描述： Digital Video Mixer(數(shù)字視頻混頻器)
中文描述： 數(shù)字視頻混合器（數(shù)字視頻混頻器）
文件頁(yè)數(shù)： 18/32頁(yè)
文件大小： 158K
代理商： TMC2081
TMC2081
PRODUCT SPECIFICATION
18
Control Register Definitions
(continued)
Output Control Register (06)
7
6
5
4
3
2
1
0
AVPIPE
Reserved
a
LUTEN
PASSON
A/BPASS
MOUT
MMSB
MFORMAT
Reg
06
Bit
7
Name
AVPIPE
Description
When LOW the pipeline latency from AV, to AVOUT is 14 CLK cycles. When
HIGH, the pipeline latency is 12 CLK cycles.
Reserved.
When LOW (write only), the
a
LUTEN is powered down. Data from
a
8-0
bypasses
the
a
LUT to control the mixer directly. When HIGH,
a
7-0
addresses the
a
LUT
which controls the mixer.
When HIGH, either PDA or PDB data may be selected to pass through the mixer
without modification. When LOW the mixer transfer function is enabled if the
PASSEN input is HIGH. The PASSON feature allows Genlock or Decoder
reference signals to be passed downstream for subsequent processing.
Selects A or B data in PASSON mode. LOW allows all pixels from PDA
23-0
during
PASSEN = LOW to pass to M
23-0
. HIGH allows all pixels from PDB
23-0
during
PASSEN = LOW to pass to M
23-0
.
Digital outputs M
23-0
are enabled when this bit is HIGH. These outputs are in a
high-impedance state when MOUT is LOW.
When LOW, the MSBs of the C
B
and C
R
M
23-0
output positions (M
15
and M
7
) are
not inverted. When HIGH, the MSBs of the C
B
and C
R
output positions are
inverted.
When LOW, 24-bit GBR or YC
B
C
R
444 output data formats are enabled. When
HIGH, the multiplexer in the M
23-0
path is enabled producing 16-bit YC
B
C
R
422.
06
06
6
5
a
LUTEN
06
4
PASSON
06
3
A/BPASS
06
2
MOUT
06
1
MMSB
06
0
MFORMAT
D/A Control Register (07)
7
6
5
4
3
2
1
0
Reserved
DACDLY
DACFMT
AWAKE
SETUP
DOVLEN
DMAT
Reg
07
07
07
Bit
7-6
5
4
Name
Description
Reserved.
Selects SYNC and BLANK pipe delay. LOW = 15 clocks, HIGH = 2 clocks.
Translates C
B
/C
R
format from 2’s complement to C
B
/C
R
offset binary. LOW
passes C
B
/C
R
unchanged. HIGH inverts C
B
/C
R
MSB.
D/A converters are enabled when HIGH. The D/A converters are powered-down
when AWAKE is LOW.
When LOW, 0 IRE blanking levels are present on the D/A converter outputs.
When HIGH, blanking levels are 7.5 IRE units.
Reserved.
When HIGH, D/A converter input data is converted from YC
B
C
R
to GBR format.
When LOW, no conversion takes place and the data is passed through.
DACDLY
DACFMT
07
3
AWAKE
07
2
SETUP
07
07
1
0
DMAT
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