參數(shù)資料
型號： TMC2081
廠商： Fairchild Semiconductor Corporation
英文描述： Digital Video Mixer(數(shù)字視頻混頻器)
中文描述： 數(shù)字視頻混合器（數(shù)字視頻混頻器）
文件頁數(shù)： 3/32頁
文件大?。?/td> 158K
代理商： TMC2081
PRODUCT SPECIFICATION
TMC2081
3
Functional Description
The TMC2081 is a monolithic digital video processor that
proportionally mixes digital video in GBR, YC
index formats. Some of the variety of input and output data
format combinations are shown in Table 1.
B
C
R
, or color-
The A-channel data path has transformation circuits that can
look up 24-bit GBR values from 8-bit color-index inputs,
convert GBR-to-YC
B
C
R
format, and decimate YC
YC
B
C
R
422. The B-channel path includes circuits that
convert YC
B
C
R
to GBR and interpolate YC
YC
B
C
R
444. Prior to mixing, incoming pixel data streams
must be converted to matching formats by setting the A and
B channel control registers.
B
C
R
444 to
B
C
R
422 to
Data enters the TMC2081 through the PDA
a
8-0
, and OL
3-0
ports. Data and video controls (PASSEN and
AV) are simultaneously registered on the rising edge of
PXCLK. Pipeline latency is 14 clock cycles to the mixed
digital video output.
23-0
, PDB
23-0
,
Although PDA
different, V
be matched: unsigned magnitude for GBR and Y
components; 2’s complement for C
23-0
, PDB
2
data formats at the
23-0
, and M
23-0
data formats may be
a
-Mixer input must
1
and V
B
and C
R
components.
Data formats converted within the TMC2081 are determined
by the control bits programmed into the internal registers.
Output format may be GBR, YC
Either crosspoint switch input, A and B or the Mixer output
may be selected at the M
23-0
port. Table 2, Table 3 and Table
4 show examples of the M
23-0
output for 9-bit
Table 3, C
B
C
R
is accepted at the C
fies format
conversion.
B
C
R
444 or YC
B
C
R
422.
a
-mixing. In
B
input. Table 4 exempli-
Mixer output and inputs may be previewed by three video
D/A converters. Analog outputs may be either GBR or
YC
B
C
R
.
For initialization and control, internal registers and tables
may be accessed through a microprocessor interface.
Power may be conserved by disabling the D/A converters or
sections of the TMC2081 via internal Control Registers.
In the latter mode, the microprocessor interface remains
active and Control Register settings are retained but CLUT
locations are not accessible.
Table 1. Input and Output Data Format Examples
Table 2. GBR Mixing Example (9-bit
a
)
A Input
Format
YC
B
C
YC
B
C
YC
B
C
YC
B
C
YC
B
C
R
422 YC
B
C
R
422 Bypass
GBR, CI
YC
B
C
R
444 Enable
GBR, CI
YC
B
C
R
444 Enable
GBR, CI
YC
B
C
R
422 Enable
GBR, CI
YC
B
C
R
422 Enable
GBR, CI
GBR
B Input
Format
C
C
C
C
A
CLUT
A
GBR-YC
Bypass
Bypass
Bypass
Bypass
Bypass
Bypass
Enable
Bypass
Enable
Bypass
B
C
R
A
Decimate
Bypass
Bypass
Enable
Bypass
Bypass
Bypass
Bypass
Bypass
Enable
Bypass
B
Interpolate
Bypass
Enable
Bypass
Bypass
Bypass
Bypass
Bypass
Enable
Bypass
Bypass
B
R
YC
B
Bypass
Bypass
Bypass
Bypass
Bypass
Enable
Bypass
Enable
Bypass
Bypass
C
-GBR
M
Format
Low
Low
High
High
Low
Low
Low
Low
High
Low
M Output
Format
YC
B
C
YC
B
C
YC
B
C
YC
B
C
YC
B
C
R
444
GBR
YC
B
C
R
444
GBR
YC
B
C
R
422
GBR
R
444 YC
444 YC
444 YC
422 YC
B
R
444 Bypass
422 Bypass
422 Bypass
422 Bypass
R
444
444
422
R
B
R
R
R
B
R
R
R
422
R
B
R
Enable
a
(hex)
000
040
080
100
PDA (hex)
B
CC
CC
CC
CC
PDB (hex)
B
FF
FF
FF
FF
M (hex)
B
FF
F2
E6
CC
G
BB
BB
BB
BB
R
AA
AA
AA
AA
G
EE
EE
EE
EE
R
G
EE
E1
D5
BB
R
DD
DD
DD
DD
DD
D0
C4
AA
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