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參數(shù)資料
| 型號(hào)： | TMC2081 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Digital Video Mixer(數(shù)字視頻混頻器) |
| 中文描述： | 數(shù)字視頻混合器（數(shù)字視頻混頻器） |
| 文件頁(yè)數(shù)： | 13/32頁(yè) |
| 文件大小： | 158K |
| 代理商： | TMC2081 |
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PRODUCT SPECIFICATION
TMC2081
13
Video Controls
PASSEN
13
TTL
Pass Enable Input.
Data selected by A/BPASS is enabled by
PASSEN.
Signal 0 Input.
Input to a 14 CLK delay. Output is at SIG14.
Pass Enable Output (14 Clock Delay).
PASSEN delayed by 14 CLK
cycles to match the pipeline latency of pixels
Signal 0 Output (14 Clock Delay).
SIG0 delayed to match the 14 CLK
cycles pipeline latency of pixels
Active Video Input.
When HIGH, AV enables data from the PDA and
PDB ports. When LOW, at the M
23-0
output, GBR data is set to zero
and YC
B
C
R
data is set to 10
h
80
h
80
h
in the offset binary format and
10
h
00
h
00
h
in 2’s complement format. In the 422 mode, AV
transitioning HIGH defines the next pixel to be the first C
B
pixel.
Delayed AV Output.
AV delayed by either 12 or 14 clock cycles.
A 14 clock cycle delay matches the pipeline delay of the A and B
channels. A 12 clock cycle delay is useful for interfacing with Fairchild
Encoders.
Sync Enable for G/Y D/A.
D/A Converter sync enable. SYNC= LOW,
disables a current source at the G/Y output, forcing the sync tip to zero
volts. SYNC = HIGH, activates the sync current at the G/Y output.
SYNC is delayed either 2 or 15 clock cycles according to the status of
the DACDLY bit. To disable sync on G/Y, ground SYNC.
Blanking Control for D/As.
D/A Converter blanking input. BLANK =
LOW disables the data and pedestal output currents. If BLANK =
HIGH, data and pedestal currents are added to the SYNC current.
BLANK is delayed either 2 or 15 clock cycles according to the status
of the DACDLY bit. For blank levels, see Tables 9, 10, 11, and 12.
SIG0
PASS14
12
123
TTL
TTL
SIG14
124
TTL
AV
14
TTL
AVOUT
122
TTL
SYNC
61
TTL
BLANK
60
TTL
Microprocessor I/O
R/W
8
TTL
Read/Write Control.
Read-Write control input. R/W controls the
direction of the D
7-0
port. If R/W = HIGH and CS is LOW, registers or
CLUTs may be read. If R/W = LOW and CS = LOW, data may be
written to control registers or CLUTs via the D
7-0
port. R/W is latched
on the falling edge of CS.
Chip Select.
Chip Select Input. If CS = HIGH, port, D
7-0
, is set to high-
impedance. If CS = LOW, port D
7-0
is enabled. Read data (R/W =
HIGH) is enabled on the falling edge of CS. Write data is latched into
the TMC2081 on the rising edge of the CS. CLUT,
a
LUT, or overlay
read/write operations require CS to be HIGH for at least 4 CLK cycles
after CS = LOW.
Register Select Controls.
Address bits input. A
2-0
select registers or
tables to be accessed (see Table 13) via D
7-0
. A
2-0
are latched on the
falling edge of CS.
Data I/O Port.
Bi-directional data port. D
0
is the LSB. Control
Registers, CLUT,
a
LUT and Overlay locations are accessed via D
7-0
.
CS
7
TTL
A
2-0
11-9
TTL
D
7-0
127,128,
1-6
TTL
Video Output
G/Y
68
1 V P-P
Green/Luminance Video.
The green/luminance analog video output.
Sync pulses are included on this output.
Blue/C
B
Video.
Blue/C
B
analog video output.
Red/C
R
Video.
Red/C
R
analog video output.
B/C
B
R/C
R
66
65
0.7 V P-P
0.7 V P-P
Pin Descriptions
(continued)
Name
Pin Number
Value
Pin Function Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2081KBC | 制造商:Rochester Electronics LLC 功能描述: |
| TMC2084 | 制造商:SMSC 制造商全稱:SMSC 功能描述:Standalone Mode CircLink Controller |
| TMC2084-HD | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC DUAL MODE CircLink Cntlr RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| TMC2084-HT | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Dual Mode CircLink Cntlr RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| TMC2084-HT-E2 | 制造商:Rochester Electronics LLC 功能描述: 制造商:SMSC 功能描述: |
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