參數(shù)資料
型號: TLV4112CDGN
元件分類: TVS-瞬態(tài)抑制二極管
英文描述: Transient Voltage Suppressor Diodes
中文描述: 電壓反饋運算放大器
文件頁數(shù): 17/22頁
文件大?。?/td> 388K
代理商: TLV4112CDGN
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289B – DECEMBER 1999 – REVISED DECEMBER 2000
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts
, the model generation software used
with Microsim PSpice
. The Boyle macromodel (see Note 3) and subcircuit in Figure 30 are generated using
the TLV411x typical electrical and operating characteristics at T
A
= 25
°
C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
NOTE 3: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits,SC-9, 353 (1974).
3
* TLV4112_5V operational amplifier ”macromodel” subcircuit
* updated using Model Editor release 9.1 on 01/18/00 at 15:50
Model Editor is an OrCAD product.
*
* connections: non–inverting input
*
| inverting input
*
| | positive power supply
*
| | | negative power supply
*
| | | | output
*
| | | | |
.subckt TLV4112_5V 1 2 3 4 5
*
c1
11
12
c2
6
7
css
10
99
dc
5
53
de
54
5
dlp
90
91
dln
92
90
dp
4
3
egnd
99
0
fb
7
99
+ 33.395E6 –1E3 1E3 33E6 –33E6
ga
6
0
gcm
0
6
2.2439E–12
10.000E–12
454.55E–15
dy
dy
dx
dx
dx
poly(2) (3,0) (4,0) 0 .5 .5
poly(5) vb vc ve vlp vln 0
11
10
12 168.39E–6
99 168.39E–12
Figure 33. Boyle Macromodel and Subcircuit
iss
hlim
ioff
j1
J2
r2
rd1
rd2
ro1
ro2
rp
rss
vb
vc
ve
vlim
vlp
vln
.model
.model
.model
.model
.ends
*$
10
90
0
11
12
6
3
3
8
7
3
10
9
3
54
7
91
0
dx
dy
jx1
jx2
4
0
6
2
1
9
11
12
5
99
4
99
0
53
4
8
0
92
D(Is=800.00E–18)
D(Is=800.00E–18 Rs=1m Cjo=10p)
NJF(Is=150.00E–12 Beta=2.0547E–3 +Vto=–1)
NJF(Is=150.00E–12 Beta=2.0547E–3 + Vto=–1)
dc
vlim 1K
dc
10 jx1
10 jx2
100.00E3
5.9386E3
5.9386E3
10
10
3.3333E3
14.493E6
dc 0
dc .86795
dc .86795
dc 0
dc 300
dc 300
13.800E–6
75E–9
IN–
G
D
S
D
S
G
rp
IN+
rd1
rd2
rss
egnd
fb
ro2
ro1
vlim
OUT
ga
ioff
gcm
vb
c1
dc
iss
dp
GND
VDD
css
c2
ve
de
dlp
dln
vln
hlim
vlp
10
4
1
11
12
53
54
9
6
8
5
7
+
91
90
92
vc
99
+
+
+
+
+
+
+
r2
2
PSpice and Partsare trademarks of MicroSim Corporation.
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