參數(shù)資料
型號(hào): TLK1221RHA
廠商: Texas Instruments, Inc.
英文描述: ETHERNET TRANSCEIVER
中文描述: 以太網(wǎng)收發(fā)器
文件頁(yè)數(shù): 9/23頁(yè)
文件大?。?/td> 501K
代理商: TLK1221RHA
www.ti.com
TRANSMITTER/RECEIVER CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
80%
50%
20%
t
r
t
r
t
f
t
f
80%
50%
20%
~
V
~
V
~
V
~
V
80%
20%
0 V
~
1 V
~
–1 V
TX+
TX–
VOD
RXP, RXN
RD(0–9)
RBC0
10-Bit Code
t
d(Rx latency)
10-Bit Code
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
TLK1221
SLLS713–FEBRUARY 2007
PARAMETER
VOD = |TxD – TxN|
Transmit common mode voltage
range
Receiver input voltage requirement,
VID = |RxP – RxN|
Receiver common mode voltage
range, (RxP + RxN)/2
Receiver input capacitance
TEST CONDITIONS
Rt = 50
MIN
600
TYP
850
MAX
1100
UNIT
mV
V
(CM)
Rt = 50
1000
1250
1400
mV
200
1600
mV
1000
1250
2250
mV
C
I
2
pF
Differential output jitter, random +
deterministic, PRBS pattern,
R
ω
= 125 MHz
Differential output jitter, PRBS
pattern, R
ω
= 125 MHz
t
(TJ)
Serial data total jitter (peak-to-peak)
0.24
UI
Serial data deterministic jitter
(peak-to-peak)
Differential signal rise, fall time (20% R
= 50
, C
L
= 5 pF, see
Figure 6
to 80%)
Serial data jitter tolerance minimum
required eye opening, (per
IEEE-802.3 specification)
Receiver data acquisition lock time
from power up
Data relock time from loss of
synchronization
Tx latency
Rx latency
t
(DJ)
0.12
UI
t
r
, t
f
100
250
ps
and
Figure 8
Differential input jitter, random +
deterministic, R
ω
= 125 MHz
0.25
UI
500
μ
s
1024
Bit times
t
d(Tx latency)
t
d(Rx latency)
See
Figure 1
See
Figure 5
and
Figure 7
20
18
22
24
UI
UI
Figure 6. Differential and Common-Mode Output Voltage Definitions
Figure 7. Receiver Latency, TBI Normal Mode Shown
9
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