參數(shù)資料
型號: TLK1221RHA
廠商: Texas Instruments, Inc.
英文描述: ETHERNET TRANSCEIVER
中文描述: 以太網(wǎng)收發(fā)器
文件頁數(shù): 2/23頁
文件大?。?/td> 501K
代理商: TLK1221RHA
www.ti.com
Differences Between TLK2201B, TLK2201BI, TLK1221, and TNETE2201
The TLK1221 is the functional equivalent of the TNETE2201. There are several differences between the devices
as noted below. Refer to
Figure 12
in the application information section for an example of a typical application
circuit.
V
CC
is 2.5 V for the TLK2201B, TLK2201BI, TLK1221, and TLK1201A vs 3.3 V for TNETE2201.
The PLL filter capacitors on pins 16, 17, 48, and 49 of the TNETE2201 are no longer required. The
TLK2201B, TLK2201BI, TLK1221, and TLK1201A use these pins to provide added test capabilities. The
capacitors, if present, do not affect the operation of the device.
No pulldown resistors are required on the TXP/TXN outputs.
The TLK1221 is a QFN version of the TLK2201B optimized for GBE-only TBI-mode operation with no JTAG
functionality.
2:1
MUX
PRBS
Generator
10 Bit
Registers
TD(0–9)
PRBSEN
LOOPEN
Parallel to
Serial
Phase Generator
Clock
REFCLK
Control
Logic
ENABLE
Interpolator
and
Clock Extraction
PRBS
Verification
Serial to Parallel
and
Comma Detect
Clock
RBC1
RBC0
SYNC/PASS
RD(0–9)
SYNCEN
2:1
MUX
2:1
MUX
Clock
Data
TXP
TXN
RXP
RXN
RBCMODE
TLK1221
SLLS713–FEBRUARY 2007
The TLK1221 is housed in a high-performance, thermally enhanced, 40-pin QFN package. Use of this package
does not require any special considerations except to note that the pad, which is an exposed die pad on the
bottom of the device, is a metallic thermal and electrical conductor. It is required that the TLK1221 pad be
soldered to the thermal land on the board as it serves as the main ground connection for the device.
The TLK1221 is characterized for operation from –40
°
C to 85
°
C.
This device uses a 2.5-V supply. The I/O section is 3.3-V compatible. With the 2.5-V supply, the chipset is very
power-efficient, dissipating less than 200 mW typical power when operating at 1.25 Gbps.
The TLK1221 is designed to be hot-plug capable. A power-on reset causes RBC0, RBC1, the parallel output
signal terminals, TXP, and TXN to be held in the high-impedance state.
Functional Block Diagram
2
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