參數(shù)資料
型號: TLK1221RHA
廠商: Texas Instruments, Inc.
英文描述: ETHERNET TRANSCEIVER
中文描述: 以太網(wǎng)收發(fā)器
文件頁數(shù): 5/23頁
文件大?。?/td> 501K
代理商: TLK1221RHA
www.ti.com
DXX.X
K28.5
DXX.X
DXX.X
K28.5
K28.5
DXX.X
DXX.X
DXX.X
DXX.X
DXX.X
K28.5
DXX.X
DXX.X
K28.5
K28.5
DXX.X
DXX.X
31 Bit
Times
Max Receive
Path Latency
Worst Case
Misaligned K28.5
Misalignment Corrected
INPUT DATA
RBC0
RBC1
RD(0–9)
SYNC
Corrupt Data
30 Bit
Times (Max)
Data Reception Latency
10-Bit Code
RXP, RXN
RD(0–9)
RBC0
10-Bit Code
t
d(Rx latency)
RBC1
Testability
TLK1221
SLLS713–FEBRUARY 2007
Figure 4. Word Realignment Timing Characteristic Waveforms
Systems that do not require framed data may disable byte alignment by tying SYNCEN low.
When a SYNC character is detected, the SYNC signal is brought high and is aligned with the K28.5 character.
The duration of the SYNC pulse is equal to the duration of the data.
The serial-to-parallel data latency is the time from when the first bit arrives at the receiver until it is output in the
aligned parallel word with RD0 received as the first bit. The minimum latency in TBI mode is 21 bit times and the
maximum latency is 31 bit times.
Figure 5. Receiver Latency, TBI Half-Rate Mode Shown
The loopback function provides for at-speed testing of the transmit/receive section of the circuitry. The enable
function allows for all circuitry to be disabled so that an Iddq test can be performed. The PRBS function also
allows for built-in self-test (BIST).
5
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