參數(shù)資料
型號(hào)： TLC320AD90CPMR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： PLASTIC, LQFP-64
文件頁(yè)數(shù)： 38/51頁(yè)
文件大?。?/td> 227K
代理商： TLC320AD90CPMR
3–8
3.4.3
Data Setup and Hold Timing
PARAMETER
MIN
TYP
MAX
UNIT
tsu1 Setup time, SDATA_IN, SDATA_OUT, SYNC valid to BIT_CLK↓
15
ns
th1
Hold time, BIT_CLK
↓ to SDATA_IN, SDATA_OUT, SYNC invalid
5
ns
3.4.4
Signal Rise and Fall Timing
PARAMETER
MIN
TYP
MAX
UNIT
tr(CLK)
Rise time, BIT_CLK
2
6
ns
tf(CLK)
Fall time, BIT_CLK
2
6
ns
tr(DIN)
Rise time, SDATA_IN
2
6
ns
tf(DIN)
Fall time, SDATA_IN
2
6
ns
tr(DOUT)
Rise time, SDATA_OUT
2
6
ns
tf(DOUT)
Fall time, SDATA_OUT
2
6
ns
tr(SYNC)
Rise time, SYNC
2
6
ns
tf(SYNC)
Fall time, SYNC
2
6
ns
3.4.5
Warm/Cold Reset Timing, TA = 25°C, AVDD = DVDD = 5 V dc,
AVSS = DVSS = 0 V, 50-pF External Load
PARAMETER
MIN
TYP
MAX
UNIT
twL(RST)
Pulse width, RESET low
1
ms
td(RST_CLK)
Delay time, RESET
↑ to BIT_CLK↑
162.8
ns
PARAMETER
MIN
TYP
MAX
UNIT
twH(SYNC)
Pulse width, SYNC high
1
1.3
ms
td(SYNC_CLK) Delay time, SYNC↓ to BIT_CLK↑
162.8
ns
3.4.6
ATE Test Mode Timing, TA = 25°C, AVDD = DVDD = 5 V dc,
AVSS = DVSS = 0 V, 50-pF External Load
PARAMETER
MIN
TYP
MAX
UNIT
tsu3
Setup time, SDATA_OUT
↑, SYNC to RESET↑ (see Notes 17
and 18)
15
ns
td(off)
Delay time, RESET
↑ to SDATA_IN, BIT_CLK Hi-Z (see
Notes 17 and 18)
25
ns
NOTES: 17. All AC-Link signals are normally low though RESET
↑. SDATA_OUT should be high prior to RESET↑ which
causes the TLC320AD90C AC-Link outputs to go high impedance which is suitable for ATE in circuit
testing.
18. The Texas Instruments internal test mode is entered by bringing SYNC high prior to RESET
↑. This mode
has no effect on the TLC320AD90C AC-Link output signal levels.
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