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參數(shù)資料
| 型號： | TLC320AD90CPMR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 24/51頁 |
| 文件大小： | 227K |
| 代理商： | TLC320AD90CPMR |
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2–16
2.4
Clocking
The TLC320AD90C codec derives its clock from an external 24.576-MHz crystal. The codec drives a
buffered and divided down (1/2) clock to the digital controller over the AC-Link on BIT_CLK. The frequency
of this clock is 12.288 MHz. (An external oscillator can be used; however, a crystal may yield more stable
operation.) See Figure 2–5 and Figure 2–6 for the clock connection options.
33 pF
XTL_IN
XTL_OUT
DVSS1
Figure 2–5. Crystal Configuration
33 pF
XTL_IN
XTL_OUT
DVSS1
50
Oscillator Output
Figure 2–6. External Oscillator Configuration
If an external oscillator is used, it must be filtered with a 33 pF capacitor and a 50
resistor.
Clock jitter at the data converters (DACs and ADCs) is a fundamental impediment to high-quality
performance. The internally generated clock provides the TLC320AD90C with a clean clock that is
independent of the physical proximity of the digital controller.
The beginning of all audio sample packets or audio frames transferred over the AC-Link are synchronized
to the rising edge of the SYNC signal. SYNC is driven by the controller. The controller receives the BIT_CLK
input and generates SYNC by dividing BIT_CLK by 256 and applying conditioning to tailor the duty cycle.
The result is a 48-kHz sample rate SYNC signal whose period defines an audio frame. Data is transferred
out on every rising edge of BIT_CLK and subsequently sampled on the receiving side of the AC-Link on each
immediately falling edge of BIT_CLK.
The audio data stream cannot be paused in record or playback since the codec does not contain data
buffering capabilities.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TLC320AD91 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Stereo Audio Codec |
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