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參數(shù)資料
| 型號： | TLC320AD55C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口) |
| 中文描述： | sigma - delta模擬接口電路（Σ-Δ模擬接口） |
| 文件頁數(shù)： | 21/41頁 |
| 文件大?。?/td> | 256K |
| 代理商： | TLC320AD55C |
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3–3
3.2
Secondary serial communication reads or writes 16-bit words that program both the options and the circuit
configurations of the device. All register programming occurs during secondary communications. Four
primary and secondary communication cycles are required to program the four registers. When the default
value for a particular register is desired, the user can omit addressing it during secondary communication.
A no-op command addresses the no-op register (register 0), and no register programming takes place
during this secondary communication.
Secondary Serial Communication
There are two methods for initiating secondary communications (see Figure 3–3):
1) by asserting a high level on FC, or 2) by asserting the LSB of DIN 16-bit serial communication high while
not in 16-bit mode (see control 1 register bit 0).
Secondary
Request
16-Bit Mode
(Control 1 Register,
Bit 0)
FC
(Hardware)
(LSB 0f DIN)
Internal TLC320AD55C
Figure 3–3. Hardware and Software Methods to Initate a Secondary Request
1.
Figures 3–5 and 3–6 show the two different methods by which FC requests secondary
communication words as well as the timing for FS, DOUT, DIN, and SCLK. The examples span
two primary communication frames. Figure 3–5 shows the use of hardware function control.
During a secondary communication, a register can be written to or read from. When writing a
value to a register, DIN contains the value to be written (see Figure 3–7). The data returned on
DOUT is 00(hex). When performing a read function, DIN can still provide data to be written to an
addressed register; however, DOUT contains the most recent value contained in the register
addressed by DIN.
DIN
(Secondary
Read)
R/W
Register Address
8 Bits
Write)
DIN
(Secondary
8 Bits
Don’t Care
Data to the
Register
Figure 3–4. Secondary DIN Format
In Figure 3–5, FC clocks in and latches on the rising edge of frame sync (FS). This causes the
start of the secondary update 32 FCLKs (see Fk divide register, Appendix A) after the start of the
primary communication frame. Read and write examples are shown for DIN and DOUT.
2.
Figure 3–6 shows the use of software function control.
The software request for function control is typically used when the required resolution of the DAC
channel is less than 16 bits. Then the least significant bit (D0) can be used for the secondary
requests as shown in Table 3–1.
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PDF描述 |
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| TLC320AD56(中文) | Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口) |
| TLC320AD56C | Sigma-Delta Analog Interface Circuit |
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相關(guān)代理商/技術(shù)參數(shù) |
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| TLC320AD56 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Analog Interface Circuit |
| TLC320AD56C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Analog Interface Circuit |
| TLC320AD56CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TLC320AD56CPT | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TLC320AD57 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
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