參數(shù)資料
型號(hào)： TL16C552AHV
廠商： Texas Instruments, Inc.
英文描述： DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO
中文描述： 雙異步通信元帶有FIFO
文件頁(yè)數(shù)： 31/39頁(yè)
文件大?。?/td> 545K
代理商： TL16C552AHV
TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
31
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
Bit 3: MSR3 is the delta data carrier detect (
DCD) bit.
DCD indicates that the DCD input to the serial
channel has changed states since the last time it was read by the CPU.
Bit 4: MSR4 is the clear-to-send (CTS) bit. CTS is the complement of the CTS input from the modem that
indicates to the serial channel that the modem is ready to receive data from SOUT. When the serial channel
is in the loop mode (MCR4 is set), MSR4 reflects the value of RTS in the MCR.
Bit 5: MSR5 is the data set ready (DSR) bit. DSR is the complement of the DSR input from the modem to
the serial channel that indicates that the modem is ready to provide received data to the serial channel
receiver circuitry. When the channel is in loop mode (MCR4 is set), MSR5 reflects the value of DTR in the
MCR.
Bit 6: MSR6 is the ring indicator (RI) bit. RI is the complement of the RI input. When the channel is in loop
mode (MCR4 is set), MSR6 reflects the value of OUT1 in the MCR.
Bit 7: MSR7 is the data carrier detect (DCD) bit. Data carrier detect indicates the status of the data carrier
detect (DCD) input. When the channel is in loop mode (MCR4 is set), MSR7 reflects the value of OUT2 in
the MCR.
Reading the MSR register clears the delta modem status indicators but has no effect on the other status bits.
For LSR and MSR, the setting of status bits is inhibited during status register read operations. If a status
condition is generated during a read IOR operation, the status bit is not set until the trailing edge of the read.
When a status bit is set during a read operation and the same status condition occurs, that status bit is
cleared at the trailing edge of the read instead of being set again. In loop back mode, when modem status
interrupts are enabled, the CTS, DSR, RI and DCD input terminals are ignored; however, a modem status
interrupt can still be generated by writing to MCR3–MCR0. Applications software should not write to the
MSR.
Table 11. Modem Status Register Bits
MSR BIT
MNEMONIC
CTS
DSR
TERI
DCD
CTS
DESCRIPTION
MSR0
Delta clear to send
MSR1
Delta data set ready
MSR2
Trailing edge of ring indicator
MSR3
Delta data carrier detect
MSR4
Clear to send
MSR5
DSR
Data set ready
MSR6
RI
Ring indicator
MSR7
DCD
Data carrier detect
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