參數資料
型號： TE28F160B3TA110
廠商： INTEL CORP
元件分類： DRAM
英文描述： 3 Volt Advanced Boot Block Flash Memory
中文描述： 1M X 16 FLASH 2.7V PROM, 110 ns, PDSO48
封裝： 12 X 20 MM, TSOP-48
文件頁數： 21/49頁
文件大小： 427K
代理商： TE28F160B3TA110
E
SMART 3 ADVANCED BOOT BLOCK
–WORD-WIDE
21
PRELIMINARY
Table 7. Status Register Bit Definition
WSMS
ESS
ES
PS
VPPS
PSS
BLS
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
(WSMS)
Check Write State Machine bit first to determine
Word Program or Block Erase completion, before
checking Program or Erase Status bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts
execution and sets both WSMS and ESS bits to
“1.” ESS bit remains set to “1” until an Erase
Resume command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erasure
0 = Successful Block Erase
When this bit is set to
“1,” WSM has applied the
max. number of erase pulses to the block and is
still unable to verify successful block erasure.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Word Program
0 = Successful Word Program
When this bit is set to “1,” WSM has attempted
but failed to program a word.
SR.3 = V
PP
STATUS (VPPS)
1 = V
PP
Low Detect, Operation Abort
0 = V
PP
OK
The V
PP
Status bit does not provide continuous
indication of V
PP
level. The WSM interrogates V
PP
level only after the Program or Erase command
sequences have been entered, and informs the
system if V
PP
has not been switched on. The V
PP
is also checked before the operation is verified by
the WSM. The V
PP
Status bit is not guaranteed to
report accurate feedback between V
PPLK
and
V
PPH
.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When Program Suspend is issued, WSM halts
execution and sets both WSMS and PSS bits to
“1.” PSS bit remains set to “1” until a Program
Resume command is issued.
SR.1 = Block Lock Status
1 = Program/Erase attempted on locked
block; Operation aborted
0 = No operation to locked blocks
If a program or erase operation is attempted to
one of the locked blocks, this bit is set by the
WSM. The operation specified is aborted and the
device is returned to read status mode.
SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
These bits are reserved for future use and should
be masked out when polling the Status Register.
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