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參數(shù)資料
| 型號(hào)： | TDA936X |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | TV signal processor-Teletext decoder with embedded m-Controller |
| 中文描述： | 電視信號(hào)處理器與嵌入式米圖文電視解碼器控制器 |
| 文件頁(yè)數(shù)： | 39/140頁(yè) |
| 文件大?。?/td> | 570K |
| 代理商： | TDA936X |
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Philips Semiconductors
Preliminary specification
1999 Sep 28
39
TV signal processor-Teletext decoder with
embedded
μ
-Controller
TDA 935X/6X/8X series
SAD DC Comparator mode
The SAD module incorporates a DC Comparator mode which is selected using the ‘DC_COMP’ control bit in
the SADB SFR. This mode enables the microcontroller to detect a threshold crossing at the input to the selected
analog input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or P3.3/ADC3) of the software ADC. A level sensitive
interrupt is generated when the analog input voltage level at the pin falls below the analog output level of the
SAD Digital-to-Analog Converter.
This mode is intended to provide the device with a wake-up mechanism from Power-down or Idle mode when
a key-press on the front panel of the TV is detected.
The following software sequence should be used when utilizing this mode for Power-down or Idle mode:
1. Disable INT1 using the IE SFR
2. Set INT1 to level sensitive using the TCON SFR
3. Set the DAC digital input level to the desired threshold level using SAD/SADB SFRs and select the required
input pin (P3.0, P3.1, P3.2 or P3,3) using CH1 and CH0 in the SAD SFR
4. Enter DC Compare mode by setting the ‘DC_COMP’ enable bit in the SADB SFR
5. Enable INT1 using the IE SFR
6. Enter Power-down/Idle mode. Upon wake-up the SAD should be restored to its conventional operating mode
by disabling the ‘DC_COMP’ control bit.
I2C Serial I/O Bus
The I
2
C bus consists of a serial data line (SDA on Port P1.7) and a serial clock line (SCL on Port P1.6).
These Ports may be enabled/disabled using TXT21.0 (I
2
C Port Enable Bit).
Within the device, two separate hardware modules utilise this Bus: The Micro-controller and the TV Signal
Processor. The Micro-controller I
2
C peripheral may operate in four different configurations:
Master Transmitter
Master Receiver
Slave Transmitter
Slave Receiver
The TV Signal Processor may be addressed in Slave Mode only, either via the 80C51 micro-controller or from
Port P1.6 and Port P1.7 by another master in the system.
I
2
C-bus control of the TV signal processor
For compatibility and possible re-use of software blocks, the I
2
C-bus control for the TV signal processor is
organised as in the stand-alone TV signal processors. The internal communication is independent of the
programming of the Ports P1.6 and P1.7. All details on the control of the TV signal processor are given in the
description of the TV signal processor.
The byte level I
2
C serial port on the device is identical in operation/configuration to the I
2
C serial port on the
8xC558, with the exception of the clock rate selection bits CR<2:0>. The operation of the I
2
C subsystem is
described in detail in the 8xC558 datasheet contained in reference [1].
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