參數(shù)資料
型號： TDA936X
廠商： NXP Semiconductors N.V.
英文描述： TV signal processor-Teletext decoder with embedded m-Controller
中文描述： 電視信號處理器與嵌入式米圖文電視解碼器控制器
文件頁數(shù)： 120/140頁
文件大?。?/td> 570K
代理商： TDA936X
1999 Sep 28
120
Philips Semiconductors
Preliminary Device Specification
TV signal processor-Teletext decoder with
embedded
μ
-Controller
TDA935X/6X/8X series
Notes
1.
When the 3.3 V supply is present and the
μ
-Controller is active a ‘low-power start-up’ mode can be activated. When
all sub-address bytes have been sent and the POR and XPR flags have been cleared the horizontal output can be
switched-on via the STB-bit (subaddress 24H). In this condition the horizontal drive signal has the nominal T
OFF
and
the T
ON
grows gradually from zero to the nominal value. As soon as the 8 V supply is present the switch-on procedure
(e.g. closing of the second loop) is continued.
On set AGC.
This parameter is not tested during production and is just given as application information for the designer of the
television receiver.
Loop bandwidth BL = 60 kHz (natural frequency fN = 15 kHz; damping factor d = 2; calculated with top sync level as
FPLL input signal level).
The IF-PLL demodulator uses an internal VCO (no external LC-circuit required) which is calibrated by means of a
digital control circuit which uses the clock frequency of the
μ
-Controller as a reference. The required IF frequency for
the various standards is set via the IFA-IFC bits in subaddress 27H. When the system is locked the resulting IF
frequency is very accurate with a deviation from the nominal value of less than 25 kHz.
This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.
Measured at 10 mV (RMS) top sync input signal.
Via this pin (38) both the demodulated IF signal and the selected CVBS (or Y+C) signal can be supplied to the output.
The selection between both signals is realised by means of the SVO bit in subaddress 22H.
So called projected zero point, i.e. with switched demodulator.
10. Measured in accordance with the test line given in Fig.49. For the differential phase test the peak white setting is
reduced to 87%.
The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and
smallest value relative to the subcarrier amplitude at blanking level.
The phase difference is defined as the difference in degrees between the largest and smallest phase angle.
2.
3.
4.
5.
6.
7.
8.
9.
B
EAM CURRENT LIMITING
,
NOTE
55
C.7.1
contrast reduction starting
voltage
voltage difference for full
contrast reduction
brightness reduction starting
voltage
voltage difference for full
brightness reduction
internal bias voltage
detection level vertical guard
minimum input current to
activate the guard circuit
maximum allowable current
3.5
V
C.7.2
2
V
C.7.3
2.5
V
C.7.4
1
V
C.7.5
C.7.6
C.7.7
3.3
3.65
tbf
V
V
mA
C.7.8
tbf
mA
F
IXED BEAM CURRENT SWITCH
-
OFF
;
NOTE
56
C.8.1
discharge current during
switch-off
discharge time of picture tube
0.85
1.0
1.15
mA
C.8.2
38
ms
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
相關(guān)PDF資料
PDF描述
TDA938X TV signal processor-Teletext decoder with embedded m-Controller
TDA9829T Downconverter For DVB(下變頻器 （DVB應(yīng)用）)
TDAT04622 TDAT SONET/SDH 155/622/2488 Mbits/s Data Interfaces
TDAT042G51A-3BLL1 TDAT SONET/SDH 155/622/2488 Mbits/s Data Interfaces
TE13004D Silicon NPN High Voltage Switching Transistor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TDA9380 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TDA938O超級芯片將微處理器(CPU)與TV信號處理器集成在一起
TDA9383 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
TDA9400 制造商:未知廠家 制造商全稱:未知廠家 功能描述:INTEGRATED CIRCUITS FOR TV AND RADIO RECEVERS
TDA9403 制造商:未知廠家 制造商全稱:未知廠家 功能描述:INTEGRATED CIRCUITS FOR TV AND RADIO RECEVERS
TDA9500 制造商:未知廠家 制造商全稱:未知廠家 功能描述:INTEGRATED CIRCUITS FOR TV AND RADIO RECEVERS
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*