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參數(shù)資料
| 型號(hào)： | TDA936X |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | TV signal processor-Teletext decoder with embedded m-Controller |
| 中文描述： | 電視信號(hào)處理器與嵌入式米圖文電視解碼器控制器 |
| 文件頁(yè)數(shù)： | 34/140頁(yè) |
| 文件大?。?/td> | 570K |
| 代理商： | TDA936X |
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Philips Semiconductors
Preliminary specification
1999 Sep 28
34
TV signal processor-Teletext decoder with
embedded
μ
-Controller
TDA 935X/6X/8X series
Interrupt Enable Structure
Each of the individual interrupt can be enable or disable by setting or clearing the relevant bit in the interrupt
enable SFR called IE. All interrupt sources can also be globally disabled by clearing the EA bit (IE.7)
The interrupt structure is shown in Figure 13.
.
Figure 13 Interrupt Structure
Interrupt Enable Priority
Each interrupt source can be assigned one of two priority levels. The interrupt priority are defined by the interrupt
priority SFR called IP. A low priority interrupt can be interrupted by a high priority interrupt, but not by another
low priority interrupt. A high priority interrupt can not be interrupted by any other interrupt source. If two requests
of different priority level are received simultaneously, the request with the highest priority level is serviced. If
requests of the same priority level are received simultaneously, an internal polling sequence determines which
request is serviced. Thus, within each priority level there is a second priority structure determined by the polling
sequence as defined in Table 9
EX0
ET0
EX1
ET1
ECC
ES2
EBUSY
H1
H2
H3
H4
H5
H6
H7
L1
L2
L3
L4
L5
L6
L7
Interrupt
Source
Source
Enable
IE.0:6
Global
Enable
IE.7
Priority
Control
IP.0:6
Highest Priority Level1
Highest Priority Level0
Lowest Priority Level1
Lowest Priority Level0
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