參數(shù)資料
型號： TDA936X
廠商： NXP Semiconductors N.V.
英文描述： TV signal processor-Teletext decoder with embedded m-Controller
中文描述： 電視信號處理器與嵌入式米圖文電視解碼器控制器
文件頁數(shù)： 18/140頁
文件大?。?/td> 570K
代理商： TDA936X
Philips Semiconductors
Preliminary specification
1999 Sep 28
18
TV signal processor-Teletext decoder with
embedded
μ
-Controller
TDA 935X/6X/8X series
The description of each of the SFR bits is shown in Table 4, The table has the SFR’s in alphabetical order.
Names
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
ACC
ACC<7>
ACC<6>
ACC<5>
ACC<4>
ACC<3>
ACC<2>
ACC<1>
ACC<0>
00H
ACC<7:0>
Accumulator value
B
B<7>
B<6>
B<5>
B<4>
B<3>
B<2>
B<1>
B<0>
00H
B<7:0>
B Register value
CCDAT1
CCD1<7>
CCD1<6>
CCD1<5>
CCD1<4>
CCD1<3>
CCD1<2>
CCD1<1>
CCD1<0>
00H
CCD1<7:0>
Closed Caption first data byte
CCDAT2
CCD2<7>
CCD2<6>
CCD2<5>
CCD2<4>
CCD2<3>
CCD2<2>
CCD2<1>
CCD2<0>
00H
CCD2<7:0>
Closed Caption second data byte
CCLIN
0
0
0
CS<4>
CS<3>
CS<2>
CS<1>
CS<0>
15H
CS<4:0>
Closed caption Slice line using 525 line number.
DPH
DPH<7>
DPH<6>
DPH<5>
DPH<4>
DPH<3>
DPH<2>
DPH<1>
DPH<0>
00H
DPH<7:0>
Data Pointer High byte, used with DPL to address auxiliary memory
DPL
DPL<7>
DPL<6>
DPL<5>
DPL<4>
DPL<3>
DPL<2>
DPL<1>
DPL<0>
00H
DPL<7:0>
Data pointer low byte, used with DPH to address auxiliary memory
IE
EA
EBUSY
ES2
ECC
ET1
EX1
ET0
EX0
00H
EA
Disable all interrupts (0), or use individual interrupt enable bits (1)
EBUSY
Enable BUSY interrupt
ES2
Enable I
2
C interrupt
ECC
Enable Closed Caption interrupt
ET1
Enable Timer 1 interrupt
EX1
Enable external interrupt 1
ET0
Enable Timer 0 interrupt
EX0
Enable External interrupt 0
IP
0
PBUSY
PES2
PCC
PT1
PX1
PT0
PX0
00H
PBUSY
Priority EBUSY interrupt
PES2
Priority ES2 Interrupt
PCC
Priority ECC interrupt
PT1
Priority Timer 1 interrupt
PX1
Priority External Interrupt 1
PT0
Priority Timer 0 interrupt
PX0
Priority External Interrupt 0
P0
-
P0<6>
P0<5>
-
-
-
-
-
FFH
P0<6:5>
Port 0 I/O register connected to external pins
P1
P1<7>
P1<6>
-
-
P1<3>
P1<2>
P1<1>
P1<0>
FFH
P1<7:6,3:0>
Port 1 I/O register connected to external pins
P2
-
-
-
-
-
-
-
P2<0>
FFH
P2<0>
Port 2 I/O register connected to external pins
Table 4 SFR Bit description
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