參數(shù)資料
型號(hào): TDA8752BH
廠商: NXP Semiconductors N.V.
英文描述: Triple high-speed Analog-to-Digital Converter 110 Msps ADC
中文描述: 三高速模擬數(shù)字轉(zhuǎn)換器110 MSPS的ADC的
文件頁數(shù): 25/36頁
文件大?。?/td> 154K
代理商: TDA8752BH
2000 Jan 10
25
Philips Semiconductors
Preliminary specification
Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)
TDA8752B
Phase-locked loop
j
PLL(p-p)
long term PLL jitter
(peak-to-peak value)
divider ratio
f
CLK
= 110 MHz;
see Table 13
0.67
ns
DR
100
4095
f
ref
reference clock frequency
range
output clock frequency range
15
280
kHz
f
PLL
t
COAST(max)
t
recap
t
cap
Φ
step
12
110
MHz
maximum coast mode time
40
lines
PLL recapture time
when coast mode is aborted
3
lines
PLL capture time
in start-up conditions
5
ms
phase shift step
T
amb
= 25
°
C
11.25
deg
ADCs
f
s
INL
maximum sampling frequency
DC integral non linearity
TDA8752B/8
from IC analog input to
digital output; ramp input;
f
CLK
= 110 MHz
from IC analog input to
digital output; ramp input;
f
CLK
= 110 MHz
from IC analog input to
digital output; 10 kHz sine
wave input; ramp input;
f
CLK
= 110 MHz; note 1
110
±
0.5
±
1.5
MHz
LSB
DNL
DC differential non linearity
±
0.5
±
1.0
LSB
ENOB
effective number of bits
7.4
bits
Signal-to-noise ratio
S/N
signal-to-noise ratio
maximum gain;
f
CLK
= 110 MHz
minimum gain;
f
CLK
= 110 MHz
45
dB
44
dB
Spurious free dynamic range
SFDR
spurious free dynamic range
maximum gain;
f
CLK
= 110 MHz
minimum gain;
f
CLK
= 110 MHz
60
dB
60
dB
Clock timing output (CKADCO, CKBO and CKAO)
η
ext
ADC clock duty cycle
f
CLK(max)
maximum clock frequency
100 MHz output
45
50
55
%
110
MHz
Clock timing input (CKEXT)
f
CLK(max)
t
CPH
t
CPL
maximum clock frequency
110
MHz
clock pulse width HIGH
3.6
ns
clock pulse width LOW
4.5
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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