- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368630 > TDA8752BH (NXP Semiconductors N.V.) Triple high-speed Analog-to-Digital Converter 110 Msps ADC PDF資料下載
參數(shù)資料
| 型號： | TDA8752BH |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Triple high-speed Analog-to-Digital Converter 110 Msps ADC |
| 中文描述： | 三高速模擬數(shù)字轉(zhuǎn)換器110 MSPS的ADC的 |
| 文件頁數(shù)： | 18/36頁 |
| 文件大小： | 154K |
| 代理商： | TDA8752BH |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
2000 Jan 10
18
Philips Semiconductors
Preliminary specification
Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)
TDA8752B
O
FFSET REGISTER
This register controls the clamp level for the
RGB channels. The relationship between the
programmingcodeandtheleveloftheclampcodeisgiven
in Table 2.
Table 2
Coding
The default programmed value is:
Programmed code = 127
Clamp code = 0
ADC output = 0.
C
OARSE AND FINE REGISTERS
These two registers enable the gain control, the AGC gain
with the coarse register and the reference voltage with the
fine register. The coarse register programming equation is
as follows:
Where: V
ref
= 2.5 V.
The gain correspondence is given in Table 3. The gain is
linear with reference to the programming code (N
FINE
= 0).
Table 3
Gain correspondence (COARSE)
The default programmed value is as follows:
N
COARSE
= 32
Gain = 0.825
V
i
to be full-scale = 1.212.
To modulate this gain, the fine register is programmed
using the above equation. With a full-scale ADC input, the
fine register resolution is a
1
2
LSB peak-to-peak
(see Table 4 for N
COARSE
= 32).
Table 4
Gain correspondence (FINE)
The default programmed value is: N
FINE
= 0.
C
ONTROL REGISTER
COAST and HSYNC signals can be inverted by setting the
I
2
C-bus control bits V level and H level respectively. When
V level and H level are set to zero respectively, COAST
and HSYNC are active HIGH.
The bit ‘edge’ defines the rising or falling edge of CKREF
to synchronise the PLL. It will be on the rising edge if the
bit is at logic 0 and on the falling edge if the bit is at logic 1.
The bits Up and Do are used for the test, to force the
charge pump current. These bits have to be logic 0 during
normal use.
The bits Ip0, Ip1 and Ip2 control the charge pump current,
to increase the bandwidth of the PLL, as shown in Table 5.
PROGRAMMED
CODE
CLAMP CODE
ADC OUTPUT
0
1
2
↓
63.5
63
62.5
↓
0
↓
63.5
64
120
↓
136
underflow
127
↓
254
255
256
↓
287
0
↓
63 or 64
64
120
↓
136
GAIN
N
1
+
V
ref
1
×
1
FINE
16
32
–
-------------------------N
16
×
N
ref
512
(
+
–
)
V
32
×
=
=
N
COARSE
GAIN
V
i
TO BE
FULL-SCALE
32
99
0.825
2.5
1.212
0.4
N
FINE
GAIN
V
i
TO BE
FULL-SCALE
0
31
0.825
0.878
1.212
1.139
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TDA8753 | YUV 8-bit analog-to-digital interface |
| TDA8753A | YUV 8-bit analog-to-digital interface |
| TDA8758 | YC8-bit Video Low-Power Analog-to-Digital Interface(YC8位視頻低功耗模數(shù)接口) |
| TDA8758G | YC 8-bit low-power analog-to-digital video interface |
| TDA8763AM | 10-bit high-speed low-power ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA8752BH/8 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple high-speed Analog-to-Digital Converter 110 Msps ADC |
| TDA8752H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple high speed Analog-to-Digital Converter ADC |
| TDA8752H/6 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple high speed Analog-to-Digital Converter ADC |
| TDA8752H/8 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple high speed Analog-to-Digital Converter ADC |
| TDA8753 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:YUV 8-bit analog-to-digital interface |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。