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參數(shù)資料
| 型號： | TDA8752BH |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Triple high-speed Analog-to-Digital Converter 110 Msps ADC |
| 中文描述： | 三高速模擬數(shù)字轉(zhuǎn)換器110 MSPS的ADC的 |
| 文件頁數(shù)： | 19/36頁 |
| 文件大小： | 154K |
| 代理商： | TDA8752BH |
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2000 Jan 10
19
Philips Semiconductors
Preliminary specification
Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)
TDA8752B
Table 5
Charge-pump current control
The default programmed value is as follows:
Charge pump current = 100
μ
A
Test bits: no test mode; bits Up and Do at logic 0
Rising edge of CKREF: bit edge at logic 0
COASTandHSYNCinputsareactiveHIGH:V leveland
H level at logic 0.
VCO
REGISTER
The bits Z2, Z1 and Z0 enable the internal resistance for
the VCO filter to be selected.
Table 6
VCO register bits
Table 7
VCO gain control
The bits V
CO1
and V
CO0
control the VCO gain.
The default programmed value is as follows:
Internal resistance = 16 k
VCO gain = 15 MHz/V.
D
IVIDER REGISTER
This register controls the PLL frequency. The bits are the
LSB bits.
The default programmed value is 0011 0010 0000 = 800.
The MSB bits (Di11, Di10 and Di9) and the LSB bit (Di0)
have to be programmed before bits Di8 to Di1 to have the
required divider ratio. The bit Di0 is used for the parity
divider number = Di0 = 0 = even number Di0 = 1 = odd
number.ItshouldbenotedthatiftheI
2
C-busprogramming
is done in mode = 1 and the bit Di0 has to be toggled, then
the registers have to be loaded twice to have the update
divider ratio.
P
OWER
-
DOWN MODE
When the supply is completely switched off, the
registersaresettotheirdefaultvalues;inthateventthey
have to be reprogrammed if the required settings are
different (e.g. through an EEPROM)
When the device is in power-down mode, the previously
programmed register values remain unaffected.
PHASEA
AND
PHASEB
REGISTERS
The bit Cka is logic 0 when the used clock is the PLL clock,
and logic 1 when the used clock is the external clock.
The bit Ckb is logic 0 when the second clock is not used.
The bits Pa4 to Pa0 and Pb4 to Pb0 are used to program
the phase shift for the clock, CKADCO, CKAO and CKBO
(see Table 8). Concerning the PHASEB register, the bit
Ckab is used to have either CKAO or CKBO at pin CKAO
(pin 81).
Ip2
Ip1
Ip0
CURRENT
(
μ
A)
6.25
12.5
25
50
100
200
400
700
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Z2
Z1
Z0
RESISTANCE
(k
)
high impedance
128
32
16
8
4
2
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V
CO1
V
CO0
VCO gain
(MHz/V)
PIXEL CLOCK
FREQUENCY
RANGE (MHz)
0
0
1
1
0
1
0
1
15
20
35
50
10 to 20
20 to 40
40 to 70
70 to 110
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相關代理商/技術(shù)參數(shù) |
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| TDA8752BH/8 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple high-speed Analog-to-Digital Converter 110 Msps ADC |
| TDA8752H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple high speed Analog-to-Digital Converter ADC |
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