參數(shù)資料
型號(hào)： TC9331F
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù)： 7/31頁(yè)
文件大小： 791K
代理商： TC9331F
TC9331F
2002-02-05
15
(2)
the control register and the I/F dedicated register
(2-1) Control register 2 (CNT-R2)
(*: Default value)
Bit
Symbol
Function
0*
Internally generated
14
LRIS1
Selects the channel clock and bit clock for the audio serial data input
from the SDI1 terminal.
1
Externally generated
0*
16 bit
13
BCIS1
Selects the bit count for the audio serial data input from the SDI1
terminal.
1
32 bit
0*
Internally generated
12
LRIS0
Selects the channel clock and bit clock for the audio serial data input
from the SDI0 terminal.
1
Externally generated
0*
16 bit
11
BCIS0
Selects the bit count for the audio serial data input from the SDI0
terminal.
1
32 bit
0*
Internally generated
10
LROS2
Selects the channel clock and bit clock for the audio serial data output
from the SDO2 terminal.
1
Externally input
0*
Internally generated
9
LROS1
Selects the channel clock and bit clock for the audio serial data output
from the SDO1 terminal.
1
Externally input
0*
16 bit (TG32)
8
BCOS1
Selects the bit clock for the audio serial data output from the SDO1
terminal.
1
32 bit (TG64)
0*
Internally generated
7
LROS0
Selects the channel clock and bit clock for the audio serial data output
from the SDO0 terminal.
1
Externally input
0*
16 bit (TG32)
6
BCOS0
Selects the bit clock for the audio serial data output from the SDO0
terminal.
1
32 bit (TG64)
Selects the mode for the SDO2 terminal bit clock output for the LR terminal and BCK terminal
output.
BCKS TOS
LR terminal output
BCK terminal output
SDO2 bit clock
0*
Internally generated
(TGLR)
Internally generated
(TG32)
Selection made at LROS2
0
1
ELRO2 input signal
EBCO2 input signal
Selection made at LROS2
1
0
Internally generated
(TGLR)
1/2 frequency of EBCO2
input signal
1/2 frequency of EBCO2
input signal
5
4
BCKS
TOS
1
ELRO2 input signal
1/2 frequency of EBCO2
input signal
1/2 frequency of EBCO2
input signal
0*
Internally generated
(TGLR)
3
SYNCS
Used to select either an internally generated or externally input (SYNC
terminal) mode.
1
External input
0*
Rise
2
SYNCP
Selects the SYNC signal polarity.
1
Fall
0*
Run
1
SYNCR1
Resets the coefficient pointer (CP) at each SYNC signal.
1
Prohibit
0*
Run
0
SYNCR0
Resets the offset address pointer (OFP) at each SYNC signal.
1
Prohibit
相關(guān)PDF資料
PDF描述
TC9331F SPECIALTY CONSUMER CIRCUIT, PQFP80
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