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參數(shù)資料
| 型號： | TC9331F |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 3/31頁 |
| 文件大?。?/td> | 791K |
| 代理商： | TC9331F |
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TC9331F
2002-02-05
11
(2)
Data output circuit
(2-1) Data output circuit
The output data is conveyed as a 2's complement expression and is the pre-padded data of the
MSB first. The SOR2 is a 16 bit fixed register while the SOR1 and SOR0 can be selected as either
16 bit or 32 bit registers. The timing signals of the SDO2, SDO1 and SDO0 output data can be
input both independently and externally to the channel clock (LRCK) and bit clock (BCK). Note
that internally generated modes are also available for the LRCK and BCK. The rising and falling
of the LRCK trailing edge is first detected and then the data is output to the PISO register.
(2-2) Data output format
The output data from the MSB database is either 16 or 32 bit. When the BCK is equal to 32 fs,
the output data is in the format shown in Figure 6. When the BCK is 64 fs, as shown in Figure 7
(a), data past the 16th bit of SDO2 is first modified then output by the LSB. Note that the data
past the 16th bit may also be modified and output by the secondary channel data LSB, depending
on the program's processing content. When the BCK input (EBCO2) of the SDO2 is set to 64s, a
clock may be set to one half the value in the BCK. In this instance, the output format will be as
shown in Figure 6. The output formats for SDO1 and SDO0 are as shown in Figure 7 (b). The
output for the LR and BCK0 terminals can be selected for either internally generated signals or
externally inputted signals.
Consequently, the LR and BCK0 output can be used as A/D and D/A converter timing signals.
When the DIR (digital audio I/F receiver) is in use, the LR and BCK0 are set up to receive
external input signals (ELRO2 and EBCO2) and to provide the D/A converter timing signals.
When the BCK of the DIR is 64 fs, and an applicable BCK of 32 fs is desired, the mode setting
and BCK input are externally output from the BCK0 at 1/2 the clock rate. This BCK0 output can
be used as a D/A converter timing signal by inputting the BCK0 output to the EBCO1 and
EBCO0.
When an A/D converter is use, the internally generated signals are used as D/A converter timing
signals.
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