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參數(shù)資料
| 型號： | TC9331F |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 30/31頁 |
| 文件大?。?/td> | 791K |
| 代理商： | TC9331F |
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TC9331F
2002-02-05
8
Figure 2
The data input/output clock selection circuit
2.
The data input and data output circuits
(1)
Data input circuit
(1-1) Data input circuit
The input data is conveyed as a 2's complement expression and corresponds to the padding
following the MSB first. The SIR1 and SIR0 input register can be selected for 16 or 32 bit data
count applications. The timing signals of the SDI1 and SDI0 input data can be input both
independently and externally to the channel clock (LRCK) and bit clock (BCK) . Note that
internally generated modes are also available for the LRCK and BCK. The rising and falling of
the LRCK trailing edge is first detected and then the input data is received internally.
(1-2) Data input format
Refer to Figures 3 and 4 (a) when the input data is 16 bit/ch.
When the BCK is at least 32 fs but not more than 64 fs, the data is received later from the
padding.
When the input data is at least 17 bit but not more than 32 bit, refer to Figures 4 (b) and 4 (c) .
The input register should be set up for 32 bit processing. As shown in Figures 4 (b) and 4 (c),
data is put into the padding and the priority bit modified before inputting. In order to input
data before it is put into the padding, the input register must be set for 32 bit and, as shown in
Figure 5, the remaining data must be reset to “zero”.
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