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參數(shù)資料
| 型號： | TC9331F |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 28/31頁 |
| 文件大?。?/td> | 791K |
| 代理商： | TC9331F |
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TC9331F
2002-02-05
6
Operating Instructions
1.
Timing sequence generating circuit.
(1)
Crystal-controlled oscillator circuit
An internal operations clock can be created by connecting a crystal-controlled oscillator (30.72 MHz),
condenser, and resistor in the manner shown in Figure 1 below.
An alternative method would be to connect a external clock to the XI terminal as shown in Figure 2
below.
Figure 1 (a)
Self excited crystal oscillator
For external clock purposes, a crystal with a good starting potential and low CI value is
recommended.
Figure 1 (b)
External clock Input
(2)
The generating circuit for the audio data input/output clock (channel clock and bit clock)
Both internal generating and external input modes are available for 16/32 bit serial data input/output
channel (LR, ELRI0-1, and ELRO0-2) and bit (BCK0, EBCI0-1, EBCO0-2) clocks.
As shown in Figure 1 (b), the channel clock is selected by LROS0-2 and LRIS0-1, and the bit clock by
BCOS0-1, BCIS0-1, and BCKS of control register 2, respectively.
Both 16 bit and 32 bit outputs are available in internal clock generation mode (SDO2 is bypassed).
The mode setup is accomplished through the microcomputer interface (control register 2).
(For further details please refer to the Explanation of the Microcomputer Interface Control Register
Functions. )
The data input (SDI1 and SDI0) channel clock and bit clock are selected by LRIS1 and LRIS0, and
BCIS1 and BCIS0 of control register 2, respectively.
Tables 1 (a) and 1 (b) below provide details regarding the data input (SDI1 and SDI0) modes.
Table 1 (a)
The (SDI1) data input channel clock and bit clock modes
Control Register 2
(CNT-R2)
Data Input Applications (SDI1)
LRIS1
BCIS1
Channel Clock/Bit Clock
Data Bit Count
0
Internally generated TGLR/(TG32/TG64)
16 bit
0
1
Internally generated TGLR/(TG32/TG64)
32 bit
1
X
External input ELRI1/EBCI1
―
Table 1 (b)
The (SDI0) data input channel clock and bit clock modes
Control Register 2
(CNT-R2)
Data Input Applications (SDI1)
LRIS0
BCIS0
Channel Clock/Bit Clock
Data Bit Count
0
Internally generated TGLR/(TG32/TG64)
16 bit
0
1
Internally generated TGLR/(TG32/TG64)
32 bit
1
X
External input ELRI0/EBCI0
―
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