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參數(shù)資料
| 型號： | TC9331F |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 26/31頁 |
| 文件大?。?/td> | 791K |
| 代理商： | TC9331F |
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TC9331F
2002-02-05
4
Description of Pin Functions
Pin
No.
Symbol
I/O
Description of Pin Function
Remark
1
PEN
I
Parity-check-function-enabling terminal. (H = enable, L = disable)
Sets up the execution of the interface data parity check (odd parity).
Pull-up resistor
2
SYNC
I
Synchronous signal input terminal.
The synchronous signal forcibly resets the program counter to “zero”, and the
polarity is set by the microcomputer controller.
Schmidt input
Pull-up resistor
3
ELRI0
For SDI0 data input
―
4
ELRI1
I
LR clock input terminal.
Input terminal for the SDI0/1 data processing LR
clock.
For SDI1 data input
―
5
ELRO0
For SDO0 data output
―
6
ELRO1
For SDO1 data output
―
7
ELRO2
I
LR clock input terminal.
Input terminal for the SDO0/1/2 data processing LR
clock.
For SDO2 data output
―
8
EBCI0
For SDI0 data input
―
9
EBCI1
I
Bit clock input terminal.
Input terminal for the SDI0/1 data processing shift
clock.
For SDI1 data input
―
10
EBCO0
For SDO0 data output
―
11
EBCO1
For SDO1 data output
―
12
EBCO2
I
Bit clock input terminal.
Input terminal for the SDO0/1/2 data processing
shift clock.
For SDO2 data output
―
14
LR
O
LR clock output terminal. (1 fs)
―
15
WCK
O
Word clock output terminal. (2 fs)
―
16
BCK0
O
Bit clock output terminal. (32 fs)
―
17
BCK1
O
Bit clock output terminal. (64 fs)
―
18
SDI0
―
19
SDI1
I
Serial data input terminals.
The microcomputer controller allows 32 bit or 16 bit input data lengths to be
selected.
―
20
SDO0
―
21
SDO1
O
Serial data output terminals.
The microcomputer controller allows 32 bit or 16 bit output data lengths to be
selected.
―
22
SDO2
O
Serial data output terminal.
Outputs 16 bit data.
―
24~31 A15~A8
O
External RAM address output terminals.
Generally used when in the pseudo-static RAM mode. In the dynamic RAM
mode, this terminal is set at “L”.
Note, however, that A8 is used for output addressing purposes in the 1 M
Dram (4 bit×256 K) mode.
―
33~40 A7~A0
O
External RAM address output terminals.
In the dynamic RAM mode, both the low and column addresses are output
from these terminals.
―
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