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參數(shù)資料
| 型號： | TC90A58F |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 36/36頁 |
| 文件大?。?/td> | 439K |
| 代理商： | TC90A58F |
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TC90A58F
2002-02-06
9
5.
HD Output
The output timing and width of HDOUT (pin 30) can be set in the I2C bus registers (see figure below).
Timing: HDSTA10~HDSTA5 in Sub-Address 05H and HDSTA4~HDSTA0 in Sub-Address 06H
Output width: HDPW10~HDPW8 in Sub-Address 06H and HDPW7~HDPW0 in Sub-Address 07H
The HD signal input from the HDIN (pin 24) can pass through unaltered and be output from HDOUT.
In this case, the HDOUT output is delayed by 15 clocks from the HDIN input.
Through Mode can be set using the HDSELB bit in the I2C bus register Sub-Address 00H.
6.
VD Output
The VD signal output from the VDIN (pin 24) can pass through unaltered and be output from VDOUT
(pin 29).
There are two output timings: output delayed by 15 clocks from VDIN or output at the same timing as
HDOUT. The timing can be selected in the I2C bus register VDOSEL Sub-Address 09H. The VD signal can
also be generated internally.
Select internal generation using the VRNMOD bit in the I2C bus register Sub-Address 02H.
MCK (APCLK)
(29.862 MHz)
HD
(INPUT)
HDOUT
HD output width
(set in I
2
C bus register)
HD output timing
(set in I
2
C bus register)
Figure 3
HDOUT Timing Chart
Figure 4
VDOUT Timing Chart
VD
(INPUT, odd field)
Odd field
HDOUT
MCK (APCLK)
(29.862 MHz)
HD (INPUT)
VDOUT
1/2H
Within 15 clocks
When VDSEL
= 0, VDSOFF = 0 and VRNMOD = 0, VD input from VDIN is
output, delayed by 15 clocks.
With all other settings, VDOUT changes with the same timing as HDOUT.
Variable (set using I
2
C bus register)
Variable (set using I
2
C bus register)
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