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參數(shù)資料
| 型號： | TC90A58F |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 24/36頁 |
| 文件大?。?/td> | 439K |
| 代理商： | TC90A58F |
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TC90A58F
2002-02-06
30
DC Characteristics
Characteristics
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Current Dissipation
IDD
200
mA
CMOS
2.4
High-level input
voltage
Schmitt
VIH
2.65
V
CMOS
0.9
Low-level input
voltage
Schmitt
VIL
0.65
V
High-level
IIH
VIN = VDD
10
10
Input current
Low-level
IIL
VIN = VSS
10
10
A
High-level
VOH
IOH = 4 mA
2.4
Output voltage
Low-level
VOL
IOH = 4 mA
0.4
V
AC Characteristics
Characteristics
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Notes
Operating frequency condition
Fclk
30
MHz
Input set-up time
ts
EXTCLK reference
1
ns
Input hold time
th
EXTCLK reference
7
ns
Clock data output phase
difference 1
tdata1
EXTCLK input
Output load
= 30 pF
0
9
ns
CKPOL
= 0
(CKOUT output
and internal
clock have Same
polarity.)
Clock data output phase
difference 2
tdata2
EXTCLK input
Output load
= 30 pF
0
7
ns
CKPOL
= 0
(CKOUT output
and internal
clock have Same
polarity.)
Clock data output phase
difference 3
tdata3
EXTCLK input
Duty
= 50%,
Output load
= 30 pF
18
9
ns
CKPOL
= 1
(CKOUT output
and internal
clock have
Opposite
polarity.)
Clock data output phase
difference 4
tdata4
EXTCLK input,
Duty
= 50%,
Output load
= 30 pF
18
10
ns
CKPOL
= 1
(CKOUT output
and internal
clock have
Opposite
polarity.)
Output signal delay time 1
tpd1
6
17
ns
CKPOL
= 0
(CKOUT output
and internal
clock have Same
polarity.)
Output signal delay time 2
tpd2
23
35
ns
CKPOL
= 1
(CKOUT output
and internal
clock have
Opposite
polarity.)
Output signal delay time 3
tpd3
8
23
ns
Output signal delay time 4
tpd4
8
22
ns
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