參數(shù)資料
型號(hào)： TC90A58F
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù)： 14/36頁(yè)
文件大?。?/td> 439K
代理商： TC90A58F
TC90A58F
2002-02-06
21
Sub-Address 0DH
Bit
7 (MSB)
6
5
4
3
2
1
0 (LSB)
Name
CLPSTA3
CLPSTA2
CLPSTA1
CLPSTA0
CLPWID10
CLPWID9
CLPWID8
CLPWID7
Default
0
CLPSTA3~CLPSTA0: Sets the starting point of the clamp pulse generated internally in Clamp Pulse
Internal Generation Mode (i.e. when CLPSEL
= 1 in Sub-Address 0EH).
This setting works in combination with the setting of CLPSTA10~CLPSTA4 in
Sub-Address 06H.
CLPWID10~CLPWID7: Sets the width of the clamp pulse generated internally in Clamp Pulse
Internal Generation Mode (i.e. when CLPSEL
= 1 in Sub-Address 0EH).
This setting works in combination with the setting of CLPWID6~CLPWID0 in
Sub-Address 0EH.
Sub-Address 0EH
Bit
7 (MSB)
6
5
4
3
2
1
0 (LSB)
Name
CLPWID6
CLPWID5
CLPWID4
CLPWID3
CLPWID2
CLPWID1
CLPWID0
CLPSEL
Default
1
0
CLPWID6~CLPWID0: Sets the width of the clamp pulse generated internally in Clamp Pulse
Internal Generation Mode (i.e. when CLPSEL
= 1 in Sub-Address 0EH).
This setting works in combination with the setting of CLPWID10~CLPWID7
in Sub-Address 0DH.
CLPSEL: Selects the externally input clamp pulse or internally generated clamp pulse.
0 (default): Externally input clamp pulse
1: Internally generated clamp pulse
Sub-Address 0FH
Bit
7 (MSB)
6
5
4
3
2
1
0 (LSB)
Name
VGTEDA9
VGTEDA8
VGTEDA7
VGTEDA6
VGTEDA5
Default
0
VGTEDA9~VGTEDA5: Sets stop point 1 of VD-noise-rejected gate pulse.
Enabled only when VGATEON in Sub-Address 11H
= 1
This setting works in combination with the setting of VGTEDA4~VGTEDA0 in
Sub-Address 10H.
Sub-Address 10H
Bit
7 (MSB)
6
5
4
3
2
1
0 (LSB)
Name
VGTEDA4
VGTEDA3
VGTEDA2
VGTEDA1
VGTEDA0
VGTEDB9
VGTEDB8
VGTEDB7
Default
0
VGTEDA4~VGTEDA0: Sets stop point 1 of VD-noise-rejected gate pulse.
VGATEON
= Enabled only when VGATEON in Sub-Address 11H = 1.
This setting works in combination with the setting of VGTEDA9~VGTEDA5 in
Sub-Address 0FH.
VGTEDB9~VGTEDB7: Sets stop point 2 of VD-noise-rejected gate pulse.
Enabled only when VGATEON in Sub-Address 11H
= 1.
This setting works in combination with the setting of VGTEDB6~VGTEDB0 in
Sub-Address 11H.
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