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參數(shù)資料
| 型號： | TC90A58F |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 3/36頁 |
| 文件大小： | 439K |
| 代理商： | TC90A58F |
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TC90A58F
2002-02-06
11
12. Built-in HPLL
The TC90A58F has a built-in horizontal PLL. The following parameters can be set using the I2C bus
registers.
Divider control (when using internal divider): DIVIIC3~DIVIIC0 in Sub-Address 14H
Can also be set using CKSEL[3:0] (pins 72~75) as well as in the I2C bus register.
CKSEL[3:0] is enabled only when DIVIIC3~DIVIIC0 in is all 0s.
Selection of phase comparator (PC) in HPLL (PC2 or PC3): PCSEL0~PCSEL1 in Sub-Address 01H
Selection of divider (internal or external): DIVSEL in Sub-Address 01H
1-Vp-p output / full-swing output (APCLK output): OUTSEL in Sub-Address 01H
HPLL oscillation/oscillation halt: HPLLSTOP in Sub-Address 01H
13. 10-Bit ADC
The TC90A58F can also be used as a 10-bit AD converter. This setting can be made using the M10B bit in
the I2C bus register Sub-Address 1CH.
Note that when the device is used as a 10-bit AD converter, only two channels (the Y and Cb signals) are
output from the following output pins.
Y signal: ROUT[7:0], GOUT[7:6]
Cb signal: GOUT[1:0], BOUT[7:0]
When the TC90A58F is used as a 10-bit AD converter, only certain functions can be used.
【
Available functions】
1.
Low-pass filter
2.
Output format setting (4:4:4 only)
3.
Y delay (Y signal only)
4.
Color bar generation (4:4:4 only)
5.
HDOUT timing adjustment
6.
VDOUT timing adjustment
8.
I2C bus register setting
9.
Countermeasure against HDIN and VDIN pulse noise
10. Countermeasure against VDIN noise
11. Clamp pulse timing
12. HPLL settings
14. Clamp level setting
【
Unavailable functions】
Processing for R601, R656, 4:1:1 and 4:2:2 modes (for functions 2, 4 and 7 in the list of available
functions shown above)
V mask
HREF
HD
VD
Dedicated
VDD
Dedicated
VSS
AVDD
AVSS
Gyrator type
DIVSEL
(ECL
PC3
PC2
PCSEL
IFIL
BFIL
AGCOFF
DIVN
HDIV
VCO1
OUTSEL
1-Vp-p sine wave
Full-scale square wave
APCLK
BUFFER
TEST
2
(div: 1896/948/880/660)
(29.82 MHz/29.82 MHz/
29.7 MHz/29.7 MHz)
(15.75/31.5/
33/45 kHz)
AGC
Figure 5
Block Diagram of HPLL
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