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參數(shù)資料
| 型號(hào)： | TC90A58F |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 439K |
| 代理商： | TC90A58F |
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TC90A58F
2002-02-06
23
Sub-Address 14H
Bit
7 (MSB)
6
5
4
3
2
1
0 (LSB)
Name
DIVIIC3
DIVIIC2
DIVIIC1
DIVIIC0
DIVHDSEL
HRESVAR
Default
0
DIVIIC3~DIVIIC0: Switches the HPLL oscillation frequency. Enabled when CKSEL[3:0] (pins 72 to
75) are all set to 0.
CKSEL[3:0] (pins 72 to 75) is enabled when DIVIIC3~DIVIIC0 is set to all 0s.
DIVIIC3
DIVIIC2
DIVIIC1
DIVIIC0
Clock Frequency
Horizontal Frequency
0
29.8 MHz
31.5 kHz, 480P
0
1
29.7 MHz
33.7 kHz, 1080I
0
1
0
29.7 MHz
45.0 kHz, 720P
0
1
27 MHz
31.5 kHz
0
1
0
29.8 MHz
15.7 kHz, 480I
0
1
0
1
0
1
0
0
1
27 MHz
15.7 kHz, general-purpose
1
0
External clock input
1
0
1
1
0
1
0
1
0
1
1
0
14.9 MHz
15.7 kHz
(Note5)
1
0
1
1
0
1
13.5 MHz
15.7 kHz
(Note6)
For Note5 and Note6, the clocks are generated by dividing the main clock by 29.8 MHz and 27 MHz
respectively.
DIVHDSEL: When using an internal HPLL, selects whether to use HDIN or the HPLL reference
signal (generated internally) as HD in the logic block.
0 (default): Uses the HPLL reference signal (internally generated) as HD in the logic block.
1: Uses HDIN as HD in the logic block.
HRESVAR: Selects whether reset values for built-in H-counters are to be set internally or externally
0 (default): The reset values are set internally.
1: The reset values can be set externally.
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