參數資料
型號： T89C5115-TISUM
廠商： Atmel
文件頁數： 26/113頁
文件大?。?/td> 0K
描述： IC 8051 MCU FLASH 16K 28SOIC
標準包裝： 27
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： UART/USART
外圍設備： POR，PWM，WDT
輸入/輸出數： 20
程序存儲器容量： 16KB（16K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數據轉換器： A/D 8x10b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
其它名稱： 89C5115-TISUM
2
AT89C5115
4128G–8051–02/08
Description
The T89C5115 is a high performance Flash version of the 80C51 single chip 8-bit micro-
controllers. It contains a 16-KB Flash memory block for program and data.
The 16-KB Flash memory can be programmed either in parallel mode or in serial mode
with the ISP capability or with software. The programming voltage is internally gener-
ated from the standard VCC pin.
The T89C5115 retains all features of the 80C52 with 256 bytes of internal RAM, a 7-
source 4-level interrupt controller and three timer/counters. In addition, the T89C5115
has a 10-bit A/D converter, a 2-KB Boot Flash memory, 2-KB EEPROM for data, a Pro-
grammable Counter Array, an XRAM of 256 bytes, a Hardware WatchDog Timer and a
more versatile serial channel that facilitates multiprocessor communication (EUART).
The fully static design of the T89C5115 reduces system power consumption by bringing
the clock frequency down to any value, even DC, without loss of data.
The T89C5115 has two software-selectable modes of reduced activity and an 8 bit clock
prescaler for further reduction in power consumption. In the idle mode the CPU is frozen
while the peripherals and the interrupt system are still operating. In the power-down
mode the RAM is saved and all other functions are inoperative.
The added features of the T89C5115 make it more powerful for applications that need
A/D conversion, pulse width modulation, high speed I/O and counting capabilities such
as industrial control, consumer goods, alarms, motor control, etc. While remaining fully
compatible with the 80C52 it offers a superset of this standard microcontroller.
In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.
Block Diagram
Note:
1. 8 analog Inputs/8 Digital I/O.
2. 2-bit I/O Port.
Timer 0
INT
RAM
256x8
T
0
T
1
R
x
D
T
x
D
XTAL2
XTAL1
UART
CPU
Timer 1
IN
T
1
Ctrl
IN
T
0
C51
CORE
P
2
(2
)
Port 1 Port 2 Port 3
Parallel I/O Ports
P
1
(1
)
P
3
XRAM
256 x 8
IB-bus
PCA
R
E
S
E
T
Watch
Dog
P
C
A
E
C
I
V
s
V
c
Timer 2
T
2
E
X
T
2
Port 4
P
4
(2
)
10-bit
ADC
Flash
16K x
8
Boot
loader
2K x 8
EE
PROM
2K x 8
V
A
V
C
V
A
R
E
F
V
A
G
N
D
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