參數(shù)資料
型號： T89C5115-TISUM
廠商： Atmel
文件頁數(shù)： 20/113頁
文件大小： 0K
描述： IC 8051 MCU FLASH 16K 28SOIC
標準包裝： 27
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： UART/USART
外圍設備： POR，PWM，WDT
輸入/輸出數(shù)： 20
程序存儲器容量： 16KB（16K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
其它名稱： 89C5115-TISUM
14
AT89C5115
4128G–8051–02/08
Clock
The T89C5115 core needs only 6 clock periods per machine cycle. This feature, called
“X2”, provides the following advantages:
Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU
power.
Saves power consumption while keeping the same CPU power (oscillator power
saving).
Saves power consumption by dividing dynamic operating frequency by 2 in
operating and idle modes.
Increases CPU power by 2 while keeping the same crystal frequency.
In order to keep the original C51 compatibility, a divider-by-2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by the software.
An extra feature is available to start after Reset in the X2 Mode. This feature can be
enabled by a bit X2B in the Hardware Security Byte. This bit is described in the section
’In-System Programming’.
Description
The X2 bit in the CKCON register (See Table 11) allows switching from 12 clock cycles
per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated
(STD mode).
Setting this bit activates the X2 feature (X2 Mode) for the CPU Clock only (See Figure
The Timers 0, 1 and 2, Uart, PCA, or watchdog switch in X2 Mode only if the corre-
sponding bit is cleared in the CKCON register.
The clock for the whole circuit and peripheral is first divided by two before being used by
the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1
input. In X2 Mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic
ratio between 40 to 60%. Figure 3. shows the clock generation block diagram. The X2
bit is validated on the XTAL1 ÷ 2 rising edge to avoid glitches when switching from the
X2 to the STD mode. Figure 4 shows the mode switching waveforms.
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