參數(shù)資料
型號(hào): T89C5115-TISUM
廠商: Atmel
文件頁(yè)數(shù): 25/113頁(yè)
文件大小: 0K
描述: IC 8051 MCU FLASH 16K 28SOIC
標(biāo)準(zhǔn)包裝: 27
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
其它名稱: 89C5115-TISUM
19
AT89C5115
4128G–8051–02/08
Table 13. Minimum Reset Capacitor for a 15k Pull-down Resistor
Note:
These values assume VDD starts from 0v to the nominal value. If the time between two
on/off sequences is too fast, the power-supply decoupling capacitors may not be fully
discharged, leading to a bad reset sequence.
During a Normal
Operation (Warm Reset)
Reset pin must be maintained for at least 2 machine cycles (24 oscillator clock periods)
to apply a reset sequence during normal operation. The number of clock periods is
mode independent (X2 or X1).
Watchdog Reset
A 1K resistor must be added in series with the capacitor to allow the use of watchdog
reset pulse output on the RST pin or when an external power-supply supervisor is used.
Figure 6 shows the reset circuitry when a capacitor is used.
Figure 6. Reset Circuitry for a Watchdog Configuration
Figure 7 shows the reset circuitry when an external reset circuit is used.
Figure 7. Reset Circuitry Example Using an External Reset Circuit
oscrst/vddrst
1ms
10ms
100ms
5ms
2.7F
4.7F
47F
20ms
10F
15F
47F
VDD
Rrst
Crst
1k
RST pin
Internal reset
watchdog
To other on-board circuitry
Reset input circuitry
VDD
Rrst
1k
RST pin
Internal reset
watchdog
To other on-board circuitry
Reset input circuitry
RST
External reset
circuit
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