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參數(shù)資料
| 型號： | T8535 |
| 廠商： | Lineage Power |
| 元件分類： | Codec |
| 英文描述： | Quad Programmable Codec(四通道可編程編解碼器) |
| 中文描述： | 四可編程編解碼器（四通道可編程編解碼器） |
| 文件頁數(shù)： | 45/54頁 |
| 文件大小： | 1872K |
| 代理商： | T8535 |
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Lucent Technologies Inc.
45
Preliminary Data Sheet
July 2000
T8535/T8536 Quad Programmable Codec
Software Interface
(continued)
Table 21. Control Bit Definition
The following table shows the control bit assignments in the memory control addresses. In all control bit cases, the
bit being set places the function into the active mode as defined in the function column.
Control Name
(Address)
HBALTAPS
(0—27, 64—91)
RESCTRL
(128)
Bit
Assignment(s)
448
Function
Balance impedance coefficients. Default value is 0x00 for all bytes except for
addresses 3 and 5, which are 0x80, and address 69, which is 0x88.
Not used, load as zeros.
A one resets all other internal states.
A one resets all control addresses to default values. Note that setting this bit
will result in it and all others of this word becoming cleared on the next PCM
frame as a normal part of the reset functionality. Alternatively, hardware reset
can be used to reset all control and state functions. It is necessary to wait at
least 256
μ
s after asserting this bit before initiating any other serial I/O trans-
actions.
Load as zeros.
Active/Standby mode. A zero causes the channel to enter standby (low-
power) mode and disables the PCM interface for this channel. A one acti-
vates the channel and the corresponding PCM bus interface. Default is zero.
Receive direction bit offset for the FS signal. Defaults to zero. These 3 bits
can be thought of as the least significant bits (RXOFF contains the more sig-
nificant bits) of a bit counter that determines the location of the first bit of the
PCM data from FS.
Load as zeros.
Receive time-slot assignment. Defaults to (16 * channel number). Each time
slot represents 8 bits.
Gain adjustment for gain transfer stage in receive direction. Defaults to
0x0400 (0 dB). This is an 11-bit multiply operation with a maximum gain of
two (6 dB). 0 dB is the maximum recommended setting.
Gain adjustment for tweak gain stage in receive direction. Defaults to 0x01ac
(
7.58 dB). This is an 11-bit multiply operation with a maximum gain of two
(6 dB). 0 dB is the maximum recommended setting.
Coefficients for the CTZ termination bleed. Defaults to 0x07ed0000.
2—7
1
0
CHACTIVE
(129)
1—7
0
RXBITOFF
(130)
5—7
0—4
0—7
RXOFF
(131)
GRX1
(132—133)
0—10
GRX2
(134—135)
0—10
CTZCTRL
(140—143)
PCMCTRL2
(145)
0—30
6—7
5
Load as zeros.
A one selects DX PCM port 1. A zero selects DX PCM port 0. Defaults to
zero. PCM port 1 is not available in all package types.
A one selects DR PCM port 1. A zero selects DR PCM port 0. Defaults to
zero. PCM port 1 is not available in all package types.
A one selects double-clocking mode. Defaults to zero (single-clocking mode).
A write to any channel affects all four channels.
A one starts transmit data on a falling BCLK edge. A zero starts transmit data
on a rising BCLK edge. Defaults to zero. A write to any channel affects all
four channels.
A one latches receive data on a rising BCLK edge. A zero latches receive
data on a falling BCLK edge. Defaults to zero. A write to any channel affects
all four channels.
A one latches FS on a rising BCLK edge. A zero latches FS on a falling BCLK
edge. Defaults to zero. A write to any channel affects all four channels.
4
3
2
1
0
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