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參數資料
| 型號： | T8535 |
| 廠商： | Lineage Power |
| 元件分類： | Codec |
| 英文描述： | Quad Programmable Codec(四通道可編程編解碼器) |
| 中文描述： | 四可編程編解碼器（四通道可編程編解碼器） |
| 文件頁數： | 1/54頁 |
| 文件大?。?/td> | 1872K |
| 代理商： | T8535 |
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Preliminary Data Sheet
July 2000
T8535/T8536 Quad Programmable Codec
Features
I
5 V operation
I
Per-channel programmable gains, equalization,
termination impedance, and hybrid balance
I
Programmable
μ
-law, or A-law modes
— Up to 256 time slots per frame
— Supports PCM data rates of 512 kbits/s to
16.384 Mbits/s
— Double-clock mode timing compatible with
ISDN standard interfaces
I
Fully programmable time-slot assignment with bit
offset
I
Analog and digital loopback test modes
I
Serial microprocessor interface
— Normal and byte-by-byte control modes
— Fast scan mode
I
Six bidirectional control leads per channel, for
SLIC and line card function control
I
Differential analog output
— Mates directly to SLICs, eliminating external
components
I
Sigma-delta converters with dither noise reduction
I
Quad design to minimize package count on dense
line card applications
I
Meets or exceeds ITU-T G.711—G.712 and rele-
vant
Telcordia Technologies
* requirements
* Telcordia Technologiesis a trademark of Bell Communications
Research, Inc.
Description
The device consists of four independent channels of
codec and digital signal processing functions on one
chip. In addition to the classic A-to-D and D-to-A con-
version, each channel provides termination imped-
ance synthesis and a hybrid balance network.
The device is controlled by a serial microprocessor
interface, and a series of bidirectional I/O leads are
provided so that this control mechanism can be uti-
lized to operate the battery feed device, ringing volt-
age switches, etc. Common data and clock paths can
be shared over any number of devices. All the filter
coefficients, signal processing, SLIC, and test fea-
tures are accessible through this interface. This
serial interface can be operated at speeds up to
4.096 Mbits/s.
The choice of a PCM bus is also programmable, with
any channel capable of being assigned to any time
slot. The PCM bus can be operated at speeds up to
16.384 Mbits/s, allowing for a maximum of 256 time
slots. Separate transmit and receive interfaces are
available for 4-wire bus designs, or they can be
strapped together for a 2-wire PCM bus.
The device is available in four packages.
The T8536 64-pin TQFP features five data latches
per channel and has two PCM ports.
The T8536 100-pin TQFP features six data latches
per channel and has two PCM ports.
The T8536 68-pin PLCC features six data latches per
channel and has one PCM port.
The T8535 44-pin PLCC has no data latches and
one PCM port.
The T8535 and the T8533 Quad Programmable Line
Card Signal Processor with Echo Cancellation are
pin compatible, as are the T8536 68-pin PLCC
device and the T8534 68-pin PLCC Quad Program-
mable Line Card Signal Processor with Echo Cancel-
lation.
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