- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383876 > T8533 (Lineage Power) Quad Programmable Line Card Signal Processor(四通道可編程線卡信號處理器) PDF資料下載
參數(shù)資料
| 型號： | T8533 |
| 廠商： | Lineage Power |
| 英文描述： | Quad Programmable Line Card Signal Processor(四通道可編程線卡信號處理器) |
| 中文描述： | 四線卡可編程信號處理器（四通道可編程線卡信號處理器） |
| 文件頁數(shù)： | 40/48頁 |
| 文件大?。?/td> | 1809K |
| 代理商： | T8533 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當(dāng)前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
Preliminary Data Sheet
July 2000
Signal Processor
T8533/34 Quad Programmable Line Card
40
Lucent Technologies Inc.
Software Interface
(continued)
Table 18. Control Bit Definitions
(continued)
Control Name
(Address)
RXBITOFF
(word 130)
Bit
Assignments
Function
5—7
Receive direction bit offset for the FS signal. Defaults to 0. These 3 bits can be
thought of as the least significant bits (RXOFF contains the more significant bits)
of a bit counter that determines the location of the first bit of the PCM data from
FS.
Load as 0.
Receive time-slot assignment. Defaults to (16 * channel number). Each time slot
represents 8 bits, allow for two time slots when using linear mode.
Gain adjustment for gain transfer stage in receive direction. Defaults to 0x0400
(0 dB). This is an 11-bit multiply operation with a maximum gain of 2 (6 dB). 0 dB
is the maximum recommended setting.
Gain adjustment for tweak gain stage in receive direction. Defaults to 0x01ac
(
7.58 dB). This is an 11-bit multiply operation with a maximum gain of 2 (6 dB).
0 dB is the maximum recommended setting.
Load as 0s.
Peak detector tweaking control. Use default of 4.
0—4
0—7
RXOFF
(word 131)
GRX1
(words
132—133)
GRX2
(words
134—135)
NORMCTRL
(word 136)
0—10
0—10
6—7
3—5
Bit Number
5
4
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Function
(dB)
0.0
3.01
6.02
9.03
12.04
15.05
18.06
21.07
Function
(dBm0)
57
54
51
48
45
42
39
36
3
0
1
0
1
0
1
0
1
0—2
Far-end speech detector threshold. Use default of 5.
Bit Number
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T8535A | Quad Programmable Codec Chip Set(四通道可編程編解碼器芯片組) |
| T8536A | Quad Programmable Codec Chip Set(四通道可編程編解碼器芯片組) |
| T8536 | Quad Programmable Codec(四通道可編程編解碼器) |
| T8535 | Quad Programmable Codec(四通道可編程編解碼器) |
| T8538A | Quad Programmable Codec(四通道可編程編解碼器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T85331G | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks |
| T85331J | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks |
| T8534 | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8533/34 Quad Programmable Line Card Signal Processor |
| T8535B | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8535B/T8536B Quad Programmable Codec |
| T8536B | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8535B/T8536B Quad Programmable Codec |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。