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參數(shù)資料
| 型號： | T8533 |
| 廠商： | Lineage Power |
| 英文描述： | Quad Programmable Line Card Signal Processor(四通道可編程線卡信號處理器) |
| 中文描述： | 四線卡可編程信號處理器（四通道可編程線卡信號處理器） |
| 文件頁數(shù)： | 37/48頁 |
| 文件大小： | 1809K |
| 代理商： | T8533 |
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Preliminary Data Sheet
July 2000
Signal Processor
T8533/34 Quad Programmable Line Card
Lucent Technologies Inc.
37
Bus Timing Diagrams
(continued)
PCM Interface
Only the first time slot is shown, and the bit offset is assumed to be zero. Notice that the PCM bus transfers the
most significant bit of the time slot first, consistent with normal telephony practice. The diagram shows a bit offset
of zero from frame strobe, and for nonzero values of RXBITOFF and TXBITOFF, the relationship between FS and
DX or DR will be shifted by the programmed number of cycles of BCLK. BCLK can be any value from 256 kHz (four
time slots) to 16.384 MHz (256 time slots). The frame strobe signal is at a rate of 8 kHz and
must
be synchronous
with the PCM bus clock (BCLK). Sixteen-bit linear code uses two consecutive time slots with LSB transmitted/
received first. See the Clocking Considerations section for the relationship between BCLK and MCLK, if used.
Figure 10 shows the PCM bus timing.
5-7188.a(F)
Figure 23. PCM Bus Timing
(Diagram shown has bit offset of zero and minimum width of FS.)
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
FS
BCLK
DX
DR
LSB
1
2
3
4
5
6
7
8
TIME SLOT 0
SIGN BIT
t
FSHOLD
t
FSSETUP
t
XDLY
t
IDHOLD
t
IDSETUP
t
FSWIDTH
ADDITIONAL
TIME SLOTS
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