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參數(shù)資料
| 型號： | T8533 |
| 廠商： | Lineage Power |
| 英文描述： | Quad Programmable Line Card Signal Processor(四通道可編程線卡信號處理器) |
| 中文描述： | 四線卡可編程信號處理器（四通道可編程線卡信號處理器） |
| 文件頁數(shù)： | 34/48頁 |
| 文件大?。?/td> | 1809K |
| 代理商： | T8533 |
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Preliminary Data Sheet
July 2000
Signal Processor
T8533/34 Quad Programmable Line Card
34
Lucent Technologies Inc.
Timing Characteristics
Table 15. Timing Characteristics
* PCM clock (BCLK) must be synchronous with both FS and MCLK, if used. If MCLK is used, then the rising edge of MCLK must coincide with
the rising edge of BCLK within 10 ns.
The t
SXBDLY
delay is from either DCLK or CS, whichever transition is later, for the first bit of the byte.
Symbol
f
DCLK
f
BCLK
Parameter
Test Conditions
—
—
Min
—
—
—
—
—
—
—
—
—
Typ
—
256
512
1024
2048
4096
8192
16384
—
Max
4096
—
—
—
—
—
—
—
100 ns in
100 ms = 1 ppm
60
60
—
Unit
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
—
Serial Bus Clock Frequency
Allowable PCM Bus Clock Fre-
quencies* (512 kHz minimum
if linear encoding is selected.)
—
Jitter of BCLK
—
—
—
Serial Bus Clock Duty Cycle
PCM Bus Clock Duty Cycle
Chip Select Setup Time, Normal
Mode
Chip Select Hold Time, Normal
Mode
Serial Bus Output Data Delay,
Normal Mode
Serial Bus Input Data Hold
Time, Normal Mode
Serial Bus Input Data Setup
Time, Normal Mode
Frame Strobe Setup Time
—
—
40
40
7
50
50
—
%
%
ns
t
CSSETUP
Serial clock frequency
= 4.096 MHz
Serial clock frequency
= 4.096 MHz
Serial clock frequency
= 4.096 MHz
Serial clock frequency
= 4.096 MHz
Serial clock frequency
= 4.096 MHz
PCM clock frequency =
16.384 MHz
PCM clock frequency =
16.384 MHz
FS synchronous with
BCLK
PCM clock frequency =
16.384 MHz
t
CSHOLD
4
—
t
DCLK
t
CSSETUP
9
ns
t
SXDLY
—
—
ns
t
SDHOLD
4
—
—
ns
t
SDSETUP
7
—
—
ns
t
FSSETUP
7
—
—
ns
t
FSHOLD
Frame Strobe Hold Time
4
—
—
ns
t
FSWIDTH
Frame Strobe Width
t
BCLK
—
125
μ
s
t
BCLK
ns
t
XDLY
PCM Bus Output Data Delay
—
—
9
ns
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