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參數(shù)資料
| 型號(hào)： | T8533 |
| 廠商： | Lineage Power |
| 英文描述： | Quad Programmable Line Card Signal Processor(四通道可編程線卡信號(hào)處理器) |
| 中文描述： | 四線卡可編程信號(hào)處理器（四通道可編程線卡信號(hào)處理器） |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 1809K |
| 代理商： | T8533 |
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24
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
Signal Processor
T8533/34 Quad Programmable Line Card
Functional Description
(continued)
Reset Functionality
(continued)
A 0.1
μ
F capacitor between the RST lead and ground
will effectively hold the lead low long enough to reset
the device on powerup, allowing for a cost-effective
power-on reset function. Notice that the memory must
be reloaded through the serial interface after a hard-
ware reset function. For proper operation, it is neces-
sary for FS and BCLK to be present and stable during
a reset. DCLK transitions (frequency is not critical as
long as the maximum rate is not exceeded) are also
required in order for all internal logic to be properly
cleared as is a wait period for the internal PLL to stabi-
lize. See the timing diagram shown in Figure 19 for the
proper hardware or power-on reset procedure.
For a software reset, the control memory should not be
accessed for a minimum of 256
μ
s following the reset.
Memory Control Mapping
Several memory locations are used to control the
device. The Software Interface tables (Table 17, Mem-
ory Mapping and Table 18, Control Bit Definition) show
the memory assignments that are useful in call pro-
cessing and system testing. It should be noted that
other memory locations are used by the device to hold
intermediate results and other device state information.
Writing to these other locations can cause serious dis-
ruptions in the operation of the device and should be
avoided.
Standby Mode
The device enters a low-power standby mode with
powerup or software reset, or by programming the
CHACTIVE register 129, bit 0. In standby mode, the
control interface is active, capable of writing or reading
registers. SLIC read and write data latches are also
active. Analog signals at VF
X
I and PCM signals at D
R
are ignored in this mode. BCLK must be present for
proper standby mode operation.
Test Capabilities
The device has several built-in test capabilities that can
be used to verify correct operation of the signal pro-
cessing of the line card. These test functions are
accessed in several different control addresses. Five
loopback modes are employed (the first four in the list
below are digital loopbacks):
Digital 1.
Allows the digital signal from the PCM bus
to be looped back to the PCM bus. This
loopback facility can be used to verify cor-
rect operation of the PCM bus interface
logic, as well as operation of the PCM
bus.
Digital 2.
Allows complete testing of the digital pro-
cessing capability of the codec by looping
the data back at the analog/digital conver-
sion interface.
Digital 3.
This loopback function is at the digital side
of the sigma-delta mode converters and
loops analog transmit data back to the
analog receive path.
Digital 4.
This loopback is at the PCM bus interface
and loops the transmit data from the line
back to the receive path.
Analog 5.
The analog loopback facility can be used
to check the operation of all the signal
processing performed in the device,
including the conversions to/from analog.
Three of these loopback functions (digital 1 and 2, and
the analog loopback) can be used with tone generation
and reception via the PCM bus.
By assigning the transmit and receive time slots identi-
cally, a loopback arrangement at the PCM bus can be
effectively programmed for signals generated on the
line side of the codec. This mode is useful for testing
from the line side through the entire device.
An optional 16-bit encoding mode is included on a per-
channel basis for use in various test scenarios, or for
use by an external digital signal processor. This mode
of operation differs from the companded modes in both
the bit order and the use of multiple time slots on the
PCM bus.
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