參數(shù)資料
型號(hào)： T7295-6
廠商： Lineage Power
英文描述： DS3/SONET STS-1 Integrated Line Receiver(DS3/SONET STS-1 集成線接收器)
中文描述： DS3/SONET STS - 1的集成線路接收器（DS3/SONET STS - 1的集成線接收器）
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 416K
代理商： T7295-6
Data Sheet
February 1997
T7295-6 DS3/SONET STS-1
Integrated Line Receiver
7
Lucent Technologies Inc.
Overview
(continued)
DS3 Signal Requirements at the DSX
(continued)
Table 3. DSX-3 Interconnection Specification
* The proposed G.703 states that the voltage in a time slot containing a zero must not exceed
residue of preceding pulses.
The power levels specified by the proposed G.703 are identical except that the power is to be measured in 3 kHz bands.
The all-1s pattern must be a pure all-1s signal, without framing or other control bits.
±
5% of the peak pulse amplitude, except for the
Table 4. DSX-3 Pulse Template Boundaries for ANSI TI.404
(See Figure 6.)
5-1242(C)r.4
Figure 6. DSX-3 Isolated Pulse Template for ANSI T1.404
Parameter
Line Rate
Line Code
Test Load
Pulse Shape
Specification
44.736 Mbits/s
Bipolar with three-0 substitution (B3ZS).
75
±
5%.
An isolated pulse must fit the template in Figure 6 or Figure 7.* The pulse amplitude may be
scaled by a constant factor to fit the template. The pulse amplitude must be between 0.36 V pk and
0.85 V pk, measured at the center of the pulse.
For an all-1s transmitted pattern, the power at 22.368 MHz
+5.7 dBm, and the power at 44.736 MHz
±
0.002 MHz must be –21.8 dBm to –14.3 dBm.
±
20 ppm.
Power Levels
±
0.002 MHz must be –1.8 dBm to
Lower Curve
Upper Curve
Time
Equation
Time
Equation
T
≤
–0.36
–0.03
T
≤
–0.68
+0.03
–0.36
≤
T
≤
+0.36
– 0.03
–0.68
≤
T
≤
+0.36
+ 0.03
+0.36
≤
T
–0.03
+0.36
≤
T
0.05 + 0.407e
–1.84[T – 0.36]
0.5 1
π
2
sin
+
1
0.18
+
–
0.5 1
π
2
sin
+
1
0.34
+
+
0.8
1.2
0.6
0.2
0.0
–0.2
–1.0
–0.5
0
0.5
1.0
1.5
N
TIME SLOTS—NORMALIZED TO PEAK LOCATION
0.4
1.0
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