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參數(shù)資料
| 型號： | T7295-6 |
| 廠商： | Lineage Power |
| 英文描述： | DS3/SONET STS-1 Integrated Line Receiver(DS3/SONET STS-1 集成線接收器) |
| 中文描述： | DS3/SONET STS - 1的集成線路接收器（DS3/SONET STS - 1的集成線接收器） |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 416K |
| 代理商： | T7295-6 |
T7295-6 DS3/SONET STS-1
Integrated Line Receiver
Data Sheet
February 1997
12
Lucent Technologies Inc.
Timing Recovery
(continued)
Jitter Transfer Characteristic
The jitter transfer characteristic indicates the fraction of
input jitter that reaches the RCLK output as a function
of input jitter frequency. Table 8 shows important jitter
transfer characteristic parameters. Figure 12 shows a
typical characteristic, with the operating conditions as
described in Table 8. Although existing standards do
not specify jitter transfer characteristic requirements,
the T7295-6 information is provided here to assist in
evaluation of the device.
5-1247(C)r.4
Figure 12. Typical PLL Jitter Transfer Characteristic
1
0
–1
–2
–3
–4
–5
100
500
1k
5k 10k
100k
500k
50k
FREQUENCY (Hz)
M
PEAK = 0.05 dB
f3dB = 205 kHz
Jitter Accommodation
Under all allowable operating conditions, the jitter
accommodation of the T7295-6 device exceeds all sys-
tem requirements for error-free operation (BER < 1e
–9
)
shown in Figure 13. The typical (V
DD
= 5.0 V, T
A
= 25
°
C,
DSX-3 nominal signal level) jitter accommodation of the
T7295-6 is also shown in Figure 13. Table 9 shows the
typical jitter tolerance for the T7295-6 at selected jitter
frequencies.
Table 9. T7295-6 Typical Jitter Tolerance
Jitter Frequency (Hz)
5 k
10 k
60 k
300 k
1 M
Jitter Amplitude (U.I.)
10
5
1
0.5
0.4
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