參數(shù)資料
型號(hào)： T7295-6
廠商： Lineage Power
英文描述： DS3/SONET STS-1 Integrated Line Receiver(DS3/SONET STS-1 集成線接收器)
中文描述： DS3/SONET STS - 1的集成線路接收器（DS3/SONET STS - 1的集成線接收器）
文件頁(yè)數(shù)： 15/20頁(yè)
文件大?。?/td> 416K
代理商： T7295-6
Data Sheet
February 1997
T7295-6 DS3/SONET STS-1
Integrated Line Receiver
15
Lucent Technologies Inc.
Timing Recovery
(continued)
Recovered Clock and Data Timing
Table 14 and Figure 14 summarize the timing relation-
ships between the high-speed logic signals RCLK,
RPDATA, and RNDATA. The duty cycle is referenced to
a V
DD
/2 threshold level. RPDATA and RNDATA change
on the rising edge of RCLK and are valid during the fall-
ing edge of RCLK. A positive pulse at the T7295-6
input creates a high level on RPDATA and a low level
on RNDATA. A negative pulse creates a high level on
RNDATA and a low level on RPDATA, and a received
zero produces low levels on both RPDATA and
RNDATA.
In-Circuit Test Capability
When pulled low, the ICT pin forces all digital output
buffers (RCLK, RPDATA, RNDATA, RLOS, RLOL pins)
into a high output impedance state. This feature allows
in-circuit testing to be done on neighboring devices
without concern for T7295-6 device buffer damage.
When forced high, the ICT pin does not affect device
operation. An internal pull-up device (nominally 50 k
)
is provided on this pin; therefore, users can leave this
pin unconnected for normal operation. Test equipment
can pull ICT low during in-circuit testing without damag-
ing the device. This is the only pin for which internal
pull-up/pull-down is provided.
Board Layout Considerations
Power Supply Bypassing
Figure 11 illustrates the recommended power supply
bypassing network. A 0.1
μ
F (C2) capacitor bypasses
the digital supplies. The analog supply V
DDA
is bypassed
by using a 0.1
μ
F (C1) capacitor and a shield bead that
removes significant amounts of high-frequency noise
generated by the system and by the device logic. Good-
quality, high-frequency (low lead inductance) capacitors
should be used. Finally, it is most important that all
ground connections be made to a low-impedance
ground plane.
Receive Input
The connections to the receive input pin must be care-
fully considered. Noise coupling must be minimized
along the path from the signal entering the board to the
input pin. Any noise coupled into the T7295-6 input
directly degrades the signal-to-noise ratio of the input
signal and may degrade sensitivity.
PLL Filter Capacitor
The PLL filter capacitor between pins LPF1 and LPF2
must be placed as close to the chip as possible (within
0.5 inches is recommended). The LPF1 and LPF2 pins
are adjacent, allowing for short-lead lengths with no
crossovers to the external capacitor. Noise coupling into
the LPF1 and LPF2 pins may degrade PLL perfor-
mance. A ceramic capacitor with the value 0.1
μ
F
±
20%
is acceptable.
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