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參數(shù)資料
| 型號： | T7295-6 |
| 廠商： | Lineage Power |
| 英文描述： | DS3/SONET STS-1 Integrated Line Receiver(DS3/SONET STS-1 集成線接收器) |
| 中文描述： | DS3/SONET STS - 1的集成線路接收器（DS3/SONET STS - 1的集成線接收器） |
| 文件頁數(shù)： | 13/20頁 |
| 文件大小： | 416K |
| 代理商： | T7295-6 |
Data Sheet
February 1997
T7295-6 DS3/SONET STS-1
Integrated Line Receiver
13
Lucent Technologies Inc.
Timing Recovery
(continued)
Jitter Accommodation
(continued)
5-1248(C)r.6
Figure 13. Input Jitter Tolerance at Nominal DSX-3 Level
40
10
1.0
0.1
1
10
100
1k
10k
100k
1000k
P
SINEWAVE JITTER FREQUENCY (Hz)
T7295-6 TYPICAL
PUB 54014
G.824
TR-TSY-000499
CATEGORY I
TR-TSY-000499
CATEGORY II
False Lock Immunity
False lock is defined as the condition where a PLL
recovered clock obtains stable phase lock at a fre-
quency not equal to the incoming data rate. The
T7295-6 device uses a combination frequency/phase-
lock architecture to prevent false lock. An on-chip fre-
quency comparator continuously compares the EXCLK
reference to the PLL clock. If the frequency difference
between the EXCLK and PLL clock exceeds approxi-
mately
±
0.5%, correction circuitry forces reacquisition
of the proper frequency and phase.
Acquisition Time
If a valid input signal is already present at the receive
input, the maximum time between the application of
device power and error-free operation is 20 ms. If
power has already been applied, the interval between
the application of valid data (or the return of valid data
following a loss of signal) and error-free operation is
4 ms.
Loss-of-Lock Detection
As stated above, the PLL acquisition aid circuitry moni-
tors the PLL clock frequency relative to the EXCLK fre-
quency. The RLOL alarm is activated if the difference
between the PLL clock and the EXCLK frequency
exceeds approximately
±
0.5%. This will not occur until
at least 250 bit periods after loss of input data.
A high RLOL output indicates that the acquisition circuit
is working to bring the PLL into proper frequency lock.
RLOL remains high until frequency lock has occurred;
however, the minimum RLOL pulse width is 32 clock
cycles.
Phase Hits
In response to a phase hit in the input data, the T7295-6
returns to error-free operation in less than 2 ms. During
the reacquisition time, RLOS may temporarily be indi-
cated.
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