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參數(shù)資料
| 型號(hào)： | T7288 |
| 廠商： | Lineage Power |
| 英文描述： | CEPT/E1 Line Interface(CEPT/E1 線接口) |
| 中文描述： | CEPT/E1線路接口（CEPT/E1線接口） |
| 文件頁數(shù)： | 16/22頁 |
| 文件大?。?/td> | 432K |
| 代理商： | T7288 |
Data Sheet
January 1998
T7288 CEPT/E1 Line Interface
16
Lucent Technologies Inc.
Timing Characteristics
All duty-cycle and timing relationships are in reference to a TTL, 1.4 V threshold level.
Loss-of-Clock Indication Timing
The clock must be absent 6.4
μ
s to guarantee a loss-of-clock indication. However, a loss-of-clock indication can
occur if the clock is absent for as little as 1.95
μ
s, depending on the timing relationship of the interruption with
respect to the timing cycle.
The returning clock must be present 3.91
μ
s to guarantee a normal condition on the loss-of-clock pin (
LOC
). How-
ever, the loss-of-clock indication can return to normal immediately, depending on the timing relationship of the sig-
nal return with respect to the timing cycle.
Table 14. Clock Timing Relationships
T
A
= –40
°
C to +85
°
C, V
DD
= 5.0 V
±
10%; load capacitance = 40 pF.
* A tolerance of
±
80 ppm.
TDATA for single-rail mode; TPDATA and TNDATA for dual-rail mode.
RDATA and VIO for single-rail mode; RPDATA and RNDATA for dual-rail mode.
Symbol
tTCLTCL
tTCHTCL
tTDVTCL
tTCLTDV
tr
tf
tRCLRCL
tRCHRDV
tRDVRCH
tRCLRDV
Description
Min
*
40
50
40
—
—
40
171
131
—
Typ
488
50
—
—
—
—
50
—
—
—
Max
*
60
—
—
40
40
60
—
—
40
Unit
ns
%
ns
ns
ns
ns
%
ns
ns
ns
TCLK Clock Period
TCLK Duty Cycle
Data Setup Time, TDATA
to TCLK
Data Hold Time, TCLK to TDATA
Clock Rise Time (10%—90%)
Clock Fall Time (10%—90%)
RCLK Duty Cycle
Data Hold Time, RCLK to RDATA, VIO
Data Setup Time, RDATA, VIO to RCLK
Propagation Delay, RCLK to RDATA, VIO
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